A 14 GHZ DELAY LOCKED LOOP WITH MINIMIZED PERIOD DELAY ERROR AND WORST 1.5% DUTY CYCLE ERROR

Abstract

In many applications, the Delay Locked Loop (DLL) is used to improve the timing margin for better performance of the synchronous system. A precise 50′ duty ratio of the clock signal is essential to the DDR SDRAM, which needs both the rising edge and the falling edge of the clock to sample the data. The duty mismatch of the output clock in the DLL may be caused by the duty error of the external input clock or by the common mode voltage offset in the voltage-controlled delay line (VCDL). Many studies have presented the duty cycle corrector (DCC) to reduce the duty mismatch of the clock. This paper proposes a high-frequency DLL that generates multiplate clocks with a wide frequency range. The object of this research is to have +-1.5% duty cycle error at the output clock and, in locked state, less than 2% of clock period delay between 0- and 360-degree phases (delay error). This generator produces 8 phases at 14 GHz.