A synthesizable pseudo fractional-N clock generator with improved duty cycle output

Abstract

A proposed synthesizable pseudo fractional-N clock generator with improved duty cycle output is presented by the pseudo fractional-N frequency synthesizer unit for SoC chips and the dynamic frequency scaling applications. The different clock frequencies can be generated by following the design flowchart. It has been fabricated in a 0.13μm CMOS technology and work with a supply voltage of 1.2V. According to measured results, the frequency range of the proposed synthesizable pseudo fractional-N clock generator is from 12.5MHz to 1GHz and the peak-to-peak jitter is less than 5% of the output period. Duty cycle error rate of the output clock frequency is 1.5% and the measured power dissipation of the pseudo fractional-N frequency synthesizer unit is 146μW at 304MHz.