GeSn has emerged as an interesting channel material for beyond 14 nm node devices, in CMOS as well as TFET configurations [1-3]. However, the advantages of sub-60mV/decade subthreshold swing (SS) due to the increased band to band tunneling in small direct-bandgap tensile-strained GeSn and higher carrier mobilities are dwarfed by the presence of traps in the gate stack. For GeSn devices, Al or Hf based high-k dielectrics have been recognized as candidates for advanced gate stacks [4-6], where the presence of the interlayer oxide (IL) has shown to decrease the interface state density, Dit [7]. However, the border traps, known to be present in the vicinity of the GeSn/Oxide interface within a few nm, can exchange charge carriers with the underlying GeSn epitaxial layer via direct tunneling of injected charge, [8-9] thus reducing the mobility and increasing SS. A detailed characterization of these border traps has not been reported so far for GeSn gate stacks. In this work, two techniques, Fourier transform deep level transient spectroscopy (FT-DLTS) and temperature derivative admittance spectroscopy (TDAS) have been used to investigate the distribution of border traps in GeSn MOS capacitors.A 40 nm nominally thick compressively strained, un-intentionally doped Ge0.092Sn0.08 layer is grown using chemical vapor deposition on a thick Ge buffer layer on Si. The GeSn surface is baked at 5000C for 30 min to remove native oxide. A complete de-oxidation is confirmed by RHEED analysis. Plasma oxidation at 1500C is then carried out for 1 nm of GeSnOx IL formation, followed by 9 nm of Al2O3 deposition at -500C. Ni dots are deposited for gate contact, followed by forming gas anneal.A broad peak at higher temperatures (~235 K) was observed in conventional FT-DLTS measurements, when MOS capacitors are pulsed from depletion (Ur=2V) to accumulation (Up=-1.5V) as shown in Figure 1a. This peak originates from traps present at the oxide interface and is absent when the device is pulsed from deep depletion to depletion (positive pulse bias). The peak corresponds to a maximum in energetic distribution of border traps, found to be present at (ΔEa = 0.36± 0.02 eV) from the valence band edge (figure 1b). The capture kinetics is studied by means of pulse filling measurement using isothermal DLTS, which exhibits an s-shaped profile. A capture cross-section, σp of ~5e-17 /cm2 is estimated. With an assumption of all states being unoccupied or occupied at the beginning of the trap filling process, the density of border trap, the tunneling depth of the traps in the oxide and the trap energy are determined. Similar results are obtained for Al2O3/GeO2/GeSn capacitors.Figure 1: (a) Conventional FT-DLTS Spectrum at quiescent reverse bias (Ur) of 2 V, trap filling pulse duration (Tp) of 100 µs, emission period width (Tw) of 51.2 ms and varying filling pulse amplitude(Up). The solid curve shows de-convoluted peaks with a Gaussian distribution for the curve corresponding to Up = -1 V. The peak at ~235K corresponds to border traps with a background distribution. The peaks at lower temperature represent bulk traps in GeSn/Ge epitaxial layers[10]. (b) Temperature derivative Admittance spectrum [11], at gate bias(Vg) of -1V. An Arrhenius plot of ln(ωpeak/T2) vs 1/kT is used to obtain activation energy of 0.36 eV from the valence band edge where ωpeak is the frequency at peak position and k is the Boltzmann constant. In conclusion, FT-DLTS and TDAS of MOS capacitors on GeSn epitaxial layers are used to study the frequency and temperature dispersion observed in the accumulation region of capacitance curves. The results are described by means of the assumption of spatially and energetically distributed states, present in the depth of the oxide which interact by tunneling and thermally activated transitions of carriers.[1] S. Wirths et al., Appl. Phys. Lett. 102, 192103(2013). [2] S. Gupta et al., VLSI Technology (VLSIT), 2012 Symposium on. IEEE, 2012.[3] Y. Yang et al., Electron Devices Meeting (IEDM), 2012 IEEE International. IEEE, 2012.[4] Y. Yang et al., Electron Devices, IEEE Transactions on 60.12 (2013): 4048-4056.[5] S. Gupta et al., Electron Devices Meeting (IEDM), 2012 IEEE International. IEEE, 2012.[6] X. Gong et al., VLSI Technology (VLSIT), 2012 Symposium on. IEEE, 2012.[7] M. Zhao et al., Appl. Phys. Lett., APL 102.14 (2013): 142906.[8] H. D. Lakhdari et al., Physical Review B, 38.18 (1988): 13124.[9] P. Van Staa et al., J. Appl. Phys., JAP 54.7 (1983): 4014-4021.[10] S. Gupta et al., ECS Transactions 53.1 (2013): 251-258.[11] V. Jian Li et al., J. Appl. Phys., JAP 109.8 (2011): 083701.
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Sep 12, 2018
G Remnev + 5
Open Access