Dual-port Memory Research Articles

Slicing FIFOs for On-Chip Memory Bandwidth Exhaustion

Within an MPSoC environment, the delivery of data from one computation stage to the next is often the bottleneck of the overall system performance. Especially in high-speed communication where at least two actors (producer and consumer) need access to the same data, the memory interface is usually the limiting factor. Therefore, many solutions like network on chips, clusters of shared memory, memory hierarchy, and so on have been proposed to transfer data from one actor to another. All solutions face the common problem that, at the lowest layer, multiple actors need simultaneous access to a hardware memory block. To avoid using dual port memory macros—which are expensive in terms of chip area—a hardware design is proposed where the communication through First-In-First-Out-Buffers (FIFOs) is transparently sliced to a set of altering memory banks. This allows simultaneous memory accesses to the same FIFO while using only single port memory macros, thus reducing on-chip area and access delay. The proposed FIFO controller balances the load of multiple FIFOs evenly over independent memory regions to maximize system performance.

Design and simulation of priority based dual port memory in quantum dot cellular automata

Design of dual port memory in QCA is an interesting field of study due to concurrent access of data from different ports, although the solution of the data conflict is a changeling task. However, Dual port memory design in QCA is reported in this paper. The architecture is based on the data priority. Priorities of the two ports are generated from the control logic block. Priority bit is required for conditions when the same memory location is requested by both of the ports and at least one operation is the write operation. The functionality of dual port memory is realized with concurrent access of memory array with parallel input-output data lines. Read–Write, Write–Write conflicts are resolved with a priority bit. Priority is uniquely calculated only when both the port request for same memory location access, i.e., the request for concurrent Read–Write or Write–Write operation. When the same memory location is selected, only the signal of the prior port is allowed and of other port is discarded. While the read operation is requested for both the port at same or different memory locations, have no data conflicts and both the ports are allowed to perform read operation. In the proposed architecture, to overcome data conflicts signals of the port having less priority are totally discarded. Significant results of Priority-based 4 × 4 dual port memory are depicted in terms of area and delay. The area, delay, and energy dissipation of Dual port QCA SRAM macro cell are 0.61 µm2, 2.0 clock cycles, and 393.9 meV, respectively. A comparative study of the proposed dual port memory in QCA, single port memory in QCA and dual port memory in CMOS are also performed in this work. The result explored that proposed dual port memory proportionately efficient with respect to the QCA single port memory as well as CMOS dual port memory in terms of area-delay-energy.

A 28-nm FD-SOI 8T Dual-Port SRAM for Low-Energy Image Processor With Selective Sourceline Drive Scheme

This paper presents a low-energy 64-Kb eight-transistor (8T) one-read/one-write dual-port image memory with a 28-nm fully depleted SOI (FD-SOI) process technology. Our proposed SRAM adopts a selective sourceline drive (SSD) scheme and a consecutive data write technique for improving active energy efficiency at low voltage. The novel SSD scheme controls sourceline voltage and eliminates leakage energy at unselected columns in read operations. We fabricated a 64-Kb 8T dual-port SRAM in the 28-nm FD-SOI process technology. The 8T SRAM cell size is $0.291 \times 1.457\,\,\mu \text{m}^{2}$ . The test chip exhibits 0.48-V operation at an access time of 135 ns. The energy minimum point is at a supply voltage of 0.56 V and an access time of 35 ns, where 265.0 fJ/cycle in write operations and 389.6 fJ/cycle in read operations are achieved. These factors are, respectively, 30% and 26% smaller than those of the 8T dual-port SRAM with the conventional scheme.

SINGLE BANK DUAL-PORT MEMORY-BASED FFT FOR FIELD PROGRAMMABLE GATE ARRAYS

A new efficient memory-based FFT calculation method is presented using dual-port memories. Algorithm mainly targets Field Programmable Gate Arrays (FPGA). A semi-in-place calculation of FFT stages is presented to have both reads and writes in a single clock while keeping the memory size equal to the FFT size. The semi- word implies that the writes are not to the original/expected position. At each intermediate calculation, the outputs are written to the position where the reads are done so that the unused data is not overwritten. Compared to multi-bank memory FFT approaches, proposed memory addressing schema is both simpler to logically establish and requires lower count of logical elements. It is shown that the proposed approach accomplishes FFT task in lowest count of clock cycles among the single bank memory-based FFT algorithms.

Fast Packet Classification using Recursive Endpoint-Cutting and Bucket Compression on FPGA

Packet classification is one of the important functions in today's high-speed Internet routers. Many existing FPGA-based approaches can achieve a high throughput but cannot accommodate the memory required for large rule tables because on-chip memory in FPGA devices is limited. In this paper, we propose a high-throughput and low-cost pipelined architecture using a new recursive endpoint-cutting (REC) decision tree. In the software environment, REC needs only 5–66% of the memory needed in Efficuts for various rule tables. Since the rule buckets associated with leaf nodes in decision trees consume a large portion of total memory, a bucket compression scheme is also proposed to reduce rule duplication. Based on experimental results on Xilinx Virtex-5/6 FPGA, the block RAM required by REC is much less than the existing FPGA-based approaches. The proposed parallel and pipelined architecture can accommodate various tables of 20 K or more rules, in the FPGA devices containing 1.6 Mb block RAM. By using dual-ported memory, throughput of beyond 100 Gbps for 40-byte packets can be achieved. The proposed architecture outperforms most FPGA-based search engines for large and complex rule tables.

Low-Leakage 3D Stacked Hybrid NEMFET-CMOS Dual Port Memory

The 3D stacked hybrid memory relies on a hysteretic Nano-Electro-Mechanical Field Effect Transistor (NEMFET) inverter to store data, and on adjacent CMOS based logic to allow for read/write operations, and data preservation. In this paper we assess the feasibility of a hybrid memory cell, and explore the design space of 3D stacked hybrid dual-port memory arrays which combine the appealing NEMFET properties, i.e., ultra-low leakage currents and abrupt switching, with the CMOS technology versatility. In the evaluation we performed a comparison in terms of footprint, access time, and energy, against state of the art CMOS dual-ports memories, considering small and large size memory arrays ( $8$ -Kbytes up to $128$ -Kbytes) implemented in various technology nodes. The 3D NEMFET-CMOS hybrid dual-port memory is on the average $25$ percent smaller and $8$ and $95$ percent larger in terms of footprint when compared to $90$ , and $45$ nm CMOS implementations, respectively. The write access time is approximately $2\times$ higher, as it is dominated by the mechanical movement of the NEMFET's suspended gate, while the read access time is about $12$ percent lower, when compared with $45$ nm CMOS counterparts. For small size memories our proposal results in at least $15$ percent and $23$ percent energy reductions for $100$ and $50$ percent data transition probability, respectively. For large size memories an energy reduction of about $40$ percent was obtained, as in this case the static energy is predominant.

A highly symmetrical 10 transistor 2-read/write dual-port static random access memory bitcell design in 28 nm high-k/metal-gate planar bulk CMOS technology

We propose a highly symmetrical 10 transistor (10T) 2-read/write (2RW) dual-port (DP) static random access memory (SRAM) bitcell in 28 nm high-k/metal-gate (HKMG) planar bulk CMOS. It replaces the conventional 8T 2RW DP SRAM bitcell without any area overhead. It significantly improves the robustness of process variations and an asymmetric issue between the true and bar bitline pairs. Measured data show that read current (Iread) and read static noise margin (SNM) are respectively boosted by +20% and +15 mV by introducing the proposed bitcell with enlarged pull-down (PD) and pass-gate (PG) N-channel MOSs (NMOSs). The minimum operating voltage (Vmin) of the proposed 256 kbit 10T DP SRAM is 0.53 V in the TT process, 25 °C under the worst access condition with read/write disturbances, and improved by 90 mV (15%) compared with the conventional one.

A time-sharing multi-channel pulse amplitude analyzer

A conventional multi-channel pulse amplitude analyzer acquires single energy spectrum, but provides no information on its tendency with time. To address the limitation, we propose a scheme of time-sharing multi-channel pulse amplitude analyzer (TSMCA). A dual-port random access memory is divided into two storage spaces, one for current energy spectrum data acquisition and another for previous energy spectrum data storage. The two tasks can be performed simultaneously, and the time-related variation tendency of energy spectrum can be obtained. A prototype system of TSMCA is designed. It performs nicely, with maximum channel number of 4096 in capacity of 232/Ch, minimal time-sharing slice of 25 ms, the differential nonlinearity of <1.5%, and the integral nonlinearity of <0.3%.

A Novel Hardware Accelerator for Embedded Object Detection Applications

Object detection applications often require the algorithms to execute on embedded processing platforms, such as multiprocessor SoCs. One way these algorithms can search input images for objects-of-interest is by consulting a detection library that contains a list of features describing the objects. The processing of large volumes of image data and consultation with a library can decrease the performance of processing platforms, as contention for cacheable resources leads to varied data locality and reuse: software-based techniques have been investigated in the literature with varied success. This paper addresses this issue head-on through a novel hardware accelerator designed to overcome the disadvantages of shared resources contention while optimizing on-chip memory consumption. Detection libraries are compressed and stored on-chip within the accelerator that decompresses the data and writes it to dedicated dual-port memories ensuring optimal library data locality and reuse for all processors. By allowing the accelerator to manipulate library data, application performance can be improved by reducing the computation carried out by processors. Our evaluation revealed that by eliminating contention within caches, the application performance was drastically improved without over-consuming on-chip resources or power.

Energy-Efficient Memory Using Magneto-Electric Switching of Ferromagnets

Recent experiments on voltage-driven magneto-electric (ME) switching of ferromagnets has shown potential for future low-energy, high-speed, nonvolatile spintronic memory. In this letter, we first analyze two different ME devices—an ME magnetic-tunnel-junction (ME-MTJ) device and an ME- xnor device—with respect to writability, readability, and switching speed. The basic operational principle of ME devices is the fact that, by applying appropriate voltage pulses on the ME oxides in contact with their respective ferromagnets, a 180° switching of the magnetization direction can be achieved. Our analysis is based on a coupled stochastic magnetization dynamics and electron transport model. Subsequently, we show that the decoupled read/write path of ME-MTJs can be utilized to construct an energy-efficient dual-port memory, which can be instrumental in improving the memory throughput. Furthermore, we also propose a novel nonvolatile, content-addressable, memory that exploits the compact xnor operation enabled by the ME- xnor device.

100-Mb/s enhanced data rate MIL-STD-1553B controller in 65-nm CMOS technology

As the demand for higher communication bandwidth in avionics increases, the need for a faster and error-free high speed 1553 bus network has become essential. Instead of installing new bus wiring, it would be useful if these buses are driven at higher data rates by retrofitting redesigned 1553 controllers. This work proposes a 100-Mb/s enhanced data rate MIL-STD-1553B controller chip in 65-nm, 1.2 V CMOS technology. The controller features an integrated remote terminal (RT), bus monitor (BM), and bus controller (BC), thus offering a complete 1553 solution at this increased throughput. Firstly, the controller incorporates a synchronous back-end and host processor interface to a true dual port memory to enable faster memory accesses. Secondly, the controller employs majority-based free-running sampling decoders, suitable to interface with 100-Mb/s analog transceivers. Finally, the enhanced 1553 control unit uses scaled-up state machines to manage the scheduling, storage, and retrieval of 1553 messages, to facilitate faster message transfer over the 1553 buses. Also, the proposed enhanced data rate controller's implementation and code testing is performed on a Spartan-6 FPGA Chipscope platform to prove its functionality for the target throughput. This prototype controller chip delivers 100 Mb/s over MIL-STD-1553B buses while consuming 29.86 mW at 100% transmitter duty cycle and occupying an area of 115470 μm2 for a target bit error rate (BER) of 10-7.

High Performance and Energy-Efficient On-Chip Cache Using Dual Port (1R/1W) Spin-Orbit Torque MRAM

This paper proposes a dual (1R/1W) port spin-orbit torque magnetic random access memory (1R/1W SOT-MRAM) for energy efficient on-chip cache applications. Our proposed dual port memory can alleviate the impact of write latency on system performance by supporting simultaneous read and write accesses. The spin-orbit device leverages the high spin current injection efficiency of spin Hall metal to achieve low critical switching current to program a magnetic tunnel junction. The low write current reduces the write power consumption, and the size of the access transistors, leading to higher integration density. Furthermore, the decoupled read and write current paths of the spin-orbit device improves oxide barrier reliability, because the write current does not flow through the oxide barrier. Device, circuit, and system level co-simulations show that a 1R/1W SOT-MRAM based L2 cache can improve the performance and energy-efficiency of the computing systems compared to SRAM and standard STT-MRAM based L2 caches.

Compact ECDSA engine for IoT applications

Security problems introduced with rapid increase in deployment of Internet-of-Things devices can be overcome only with lightweight cryptographic schemes and modules. A compact prime field (GF(p)) elliptic curve digital signature algorithm (ECDSA) engine suitable for use in such applications is presented. Generic architecture of the engine makes it suitable for other elliptic curve (EC) based schemes (EC Diffie–Hellman key exchange, EC integrated encryption, EC factoring etc.) with slight modifications. The presented engine is composed of a simple microcoded controller and application-specific processing units. It can work with ECs of up to 256 bits, while 160-bit ECDSA signature generation takes 490 K cycles. The engine is implemented as an intellectual property (IP) in a 180 nm process. However, its architecture allows it to be implemented on any application specific integrated circuit (ASIC) or FPGA platform with dual-port memory support. In view of its gate count of 11,366 gate equivalents, the presented work is the most compact ECDSA engine with capability for a wide range of curves and different applications.

Argo: A Real-Time Network-on-Chip Architecture With an Efficient GALS Implementation

In this paper, we present an area-efficient, globally asynchronous, locally synchronous network-on-chip (NoC) architecture for a hard real-time multiprocessor platform. The NoC implements message-passing communication between processor cores. It uses statically scheduled time-division multiplexing (TDM) to control the communication over a structure of routers, links, and network interfaces (NIs) to offer real-time guarantees. The area-efficient design is a result of two contributions: 1) asynchronous routers combined with TDM scheduling and 2) a novel NI microarchitecture. Together they result in a design in which data are transferred in a pipelined fashion, from the local memory of the sending core to the local memory of the receiving core, without any dynamic arbitration, buffering, and clock synchronization. The routers use two-phase bundled-data handshake latches based on the Mousetrap latch controller and are extended with a clock gating mechanism to reduce the energy consumption. The NIs integrate the direct memory access functionality and the TDM schedule, and use dual-ported local memories to avoid buffering, flow-control, and synchronization. To verify the design, we have implemented a 4 $\times $ 4 bitorus NoC in 65-nm CMOS technology and we present results on area, speed, and energy consumption for the router, NI, NoC, and postlayout.

High-Performance and Dynamically Updatable Packet Classification Engine on FPGA

High-performance and dynamically updatable hardware architectures for multi-field packet classification have regained much interest in the research community. For example, software defined networking requires 15 fields of the packets to be checked against a predefined rule set. Many algorithmic solutions for packet classification have been studied over the past decade. FPGA-based packet classification engines can achieve very high throughput; however, supporting dynamic updates is yet challenging. In this paper, we present a two-dimensional pipelined architecture for packet classification on FPGA; this architecture achieves high throughput while supporting dynamic updates. In this architecture, modular Processing Elements (PEs) are arranged in a two-dimensional array. Each PE accesses its designated memory locally, and supports prefix match and exact match efficiently. The entire array is both horizontally and vertically pipelined. We exploit striding, clustering, dual-port memory, and power gating techniques to further improve the performance of our architecture. The total memory is proportional to the rule set size. Our architecture sustains high clock rate even if we scale up (1) the length of each packet header, or/and (2) the number of rules in the rule set. The performance of the entire architecture does not depend on rule set features such as the number of unique values in each field. The PEs are also self-reconfigurable; they support dynamic updates of the rule set during run-time with very little throughput degradation. Experimental results show that, for a 1 K 15-tuple rule set, a state-of-the-art FPGA can sustain a throughput of 650 Million Packets Per Second (MPPS) with 1 million updates/second. Compared to TCAM, our architecture demonstrates at least four-fold energy efficiency while achieving two-fold throughput.

On the Implementation of Time-Multiplexed Frequency-Response Masking Filters

The complexity of narrow transition band FIR filters is high and can be reduced by using frequency-response masking (FRM) techniques. These techniques use a combination of periodic model filters and, possibly periodic, masking filters. Time-multiplexing is in general beneficial since only rarely does the technology bound maximum obtainable clock frequency and the application determined required sample rate correspond. Therefore, architectures for time-multiplexed FRM filters that benefit from the inherent sparsity of the periodic filters are introduced in this paper. We show that FRM filters not only reduce the number of multipliers needed, but also have benefits in terms of memory usage. Despite the total amount of samples to be stored is larger for FRM, it results in fewer memory resources needed in FPGAs and more energy efficient memory schemes in ASICs. In total, the power consumption is significantly reduced compared with a single-stage implementation. Furthermore, we show that the choice of the interpolation factor that gives the least complexity for the periodic model filter and subsequent masking filter(s) is a function of the time-multiplexing factor, meaning that the minimum number of multipliers not always corresponds to the minimum number of multiplications. Both single-port and dual-port memories are considered, and the involved tradeoff in number of multipliers and memory complexity is illustrated. The results show that, for FPGA implementation, the power reduction ranges from 23% to 68% for the considered examples.

ARC 2014

The embedded image processing systems like smartphones and digital cameras have tight limits on storage, computation power, network connectivity, and battery usage. These limitations make it important to ensure efficient image coding. In the article, we present a novel heap-based priority queue structure employed by an Adaptive Scanning of Wavelet Data scheme (ASWD) targeting an embedded platform. ASWD is a context modeling block implemented via priority queues in a wavelet-based image coder to reorganize the wavelet coefficients into locally stationary sequences. The architecture we propose exploits efficient use of FPGA’s on-chip dual-port memories in an adaptive manner. Innovations of index-aware system linked to each element in the queue makes the location of queue element traceable in the heap as per the requirements of the ASWD algorithm. Moreover, use of 4-port memories along with intelligent data concatenation of queue elements yielded in a cost effective enhanced memory access. The memory ports are adaptively assigned to different units during different processing phases in a manner to optimally take advantage of memory access required by that phase. The architectural innovations can also be exploited in other applications that require efficient hardware implementations of generic priority queue or classical sorting applications which sort into the index. We designed and validated the hardware on an Altera’s Stratix IV FPGA as an IP accelerator in a Nios II processor based System on Chip. We show that our architecture at 150MHz can provide 45X speedup compared to an embedded ARM Cortex-A9 processor at 666MHz targeting the throughput of 10MB/s.

Efficient Memory-Addressing Algorithms for FFT Processor Design

This paper explores efficient memory management schemes for memory-based architectures of the fast Fourier transform (FFT). A data relocation scheme that merges multiple banks to lower the area requirement and power dissipation of memory-based FFT architectures is proposed. The proposed memory-addressing method can effectively deal with single-port, merged-bank memory with high-radix processing elements. Compared with conventional memory-based FFT designs using dual-port memory, the derived architecture has better performance in terms of area and power consumption. The proposed scheme is extended to a cached-memory FFT architecture to further reduce power dissipation. An 8192-point cached-memory FFT processor is implemented for digital video broadcasting-terrestrial/handheld applications by using 0.18- $\mu $ m 1P6M CMOS technology. Experimental results show that the proposed memory scheme consumes 10.1%–29.3% less area and 9.6%–67.9% less power compared with those of the multibank design.

Spin-Hall Magnetic Random-Access Memory With Dual Read/Write Ports for On-Chip Caches

This paper proposes two types of dual-ported (1-read/1-write: 1R/1W) spin-Hall magnetic random-access memory (SH-MRAM) suitable for on-chip cache applications. Separate write and read ports allow simultaneous write and read access, which can mitigate the impact of slow write latency on the system performance without any area overhead compared to the single-ported SH-MRAM. The efficient spin-Hall effect based spin-transfer torque (STT) leads to low-power write operation. In addition, separate read and write current paths of the devices can enhance the read operation without much impact on the write operation. The differential sensing scheme in 1R/1W differential SH-MRAM can further improve sensing power and sensing margin. Compared to the 1R/1W STT-MRAM bit cell, the 1R/1W SH-MRAM bit cell can achieve lower power consumption for write operation and higher sensing margin with low read power consumption under an iso-area condition.

A dual-port eight-transistor static memory cell with improved noise immunity

The results of simulation and measured parameters of a dual-selective static random access memory cell with two address inputs implemented in 180-nm CMOS technology are presented. Dependences of the static noise margin (SNM), write margin (WRM), noise margin at separate control nodes, and digit current on the potential of the trigger common bus are investigated. An increase in the SNM by 26% (up to 222 mV) and in the WRM by 6% (up to 1017 mV) as compared to the known circuit is obtained.