Design and simulation of priority based dual port memory in quantum dot cellular automata

Abstract

Design of dual port memory in QCA is an interesting field of study due to concurrent access of data from different ports, although the solution of the data conflict is a changeling task. However, Dual port memory design in QCA is reported in this paper. The architecture is based on the data priority. Priorities of the two ports are generated from the control logic block. Priority bit is required for conditions when the same memory location is requested by both of the ports and at least one operation is the write operation. The functionality of dual port memory is realized with concurrent access of memory array with parallel input-output data lines. Read–Write, Write–Write conflicts are resolved with a priority bit. Priority is uniquely calculated only when both the port request for same memory location access, i.e., the request for concurrent Read–Write or Write–Write operation. When the same memory location is selected, only the signal of the prior port is allowed and of other port is discarded. While the read operation is requested for both the port at same or different memory locations, have no data conflicts and both the ports are allowed to perform read operation. In the proposed architecture, to overcome data conflicts signals of the port having less priority are totally discarded. Significant results of Priority-based 4 × 4 dual port memory are depicted in terms of area and delay. The area, delay, and energy dissipation of Dual port QCA SRAM macro cell are 0.61 µm2, 2.0 clock cycles, and 393.9 meV, respectively. A comparative study of the proposed dual port memory in QCA, single port memory in QCA and dual port memory in CMOS are also performed in this work. The result explored that proposed dual port memory proportionately efficient with respect to the QCA single port memory as well as CMOS dual port memory in terms of area-delay-energy.