A dual-port eight-transistor static memory cell with improved noise immunity

Abstract

The results of simulation and measured parameters of a dual-selective static random access memory cell with two address inputs implemented in 180-nm CMOS technology are presented. Dependences of the static noise margin (SNM), write margin (WRM), noise margin at separate control nodes, and digit current on the potential of the trigger common bus are investigated. An increase in the SNM by 26% (up to 222 mV) and in the WRM by 6% (up to 1017 mV) as compared to the known circuit is obtained.