Slicing FIFOs for On-Chip Memory Bandwidth Exhaustion

Abstract

Within an MPSoC environment, the delivery of data from one computation stage to the next is often the bottleneck of the overall system performance. Especially in high-speed communication where at least two actors (producer and consumer) need access to the same data, the memory interface is usually the limiting factor. Therefore, many solutions like network on chips, clusters of shared memory, memory hierarchy, and so on have been proposed to transfer data from one actor to another. All solutions face the common problem that, at the lowest layer, multiple actors need simultaneous access to a hardware memory block. To avoid using dual port memory macros—which are expensive in terms of chip area—a hardware design is proposed where the communication through First-In-First-Out-Buffers (FIFOs) is transparently sliced to a set of altering memory banks. This allows simultaneous memory accesses to the same FIFO while using only single port memory macros, thus reducing on-chip area and access delay. The proposed FIFO controller balances the load of multiple FIFOs evenly over independent memory regions to maximize system performance.