Dual-gate Organic Thin-film Transistors Research Articles

High-speed, low-voltage, small-pitch and robust OTFT-based integrated gate driver for active-matrix displays

We design and fabricate a high-speed, low-voltage, small-pitch, and robust integrated gate driver with organic thin-film transistors (OTFTs). The dual-gate OTFT devices have a field effect mobility of 0.78 cm2/Vs, and on/off current ratio above 108. A single stage of the gate driver consists of ten TFTs and two capacitors, with small pitch of 244 μm. The fabricated circuit has a minimum pulse width of 5μs, which is compatible with full-high definition (FHD, 1920 × 1080) active-matrix displays with 60Hz frame rate. It can work at input swing of as low as 10V, with VGH2, VGH1, and VGL of 5V, 0V, and −10V respectively. With the threshold voltage shift under positive and negative bias stress, the gate driver shows output signals without significant degradation and demonstrates its high reliability through simulation.

Carrier confinement for mobility enhancement in dual-gate organic thin-film transistors

Mobility of charge carriers in organic thin-film transistors (OTFTs) is one of the most important parameters, which is affected by the disorders in the semiconducting films. In general, realization of higher carrier concentration facilitates improved charge transport against these disorders. Here, we demonstrate in amorphous indacenodithiophen-co-benzothiadia (IDT-BT) based dual-gate organic thin-film transistors (DG-OTFTs) that the mobility can be robustly increased from 0.8 to 1.37 cm2 V−1 s−1, when voltage biases of opposite signs (negative one accumulate holes, positive one deplete holes) are applied on the dual independent gate electrodes. In details, the positive bias can confine the spatial distribution of the accumulated carriers near the negatively biased gate, leading to a higher effective carrier concentration with higher mobility. In addition, the interface confinement effect of carriers was further verified by two-dimensional numerical simulation, and calculations based on the variable range hopping method were performed to accurately reproduce the experimentally observed charge transport behavior in DG-OTFTs.

Dual-Gate Organic Thin-Film Transistor and Multiplexer Chips for the Next Generation of Flexible EG-ISFET Sensor Chips.

Ion-sensitive field-effect transistors (ISFETs) are used as elementary devices to build many types of chemical sensors and biosensors. Organic thin-film transistor (OTFT) ISFETs use either small molecules or polymers as semiconductors together with an additive manufacturing process of much lower cost than standard silicon sensors and have the additional advantage of being environmentally friendly. OTFT ISFETs' drawbacks include limited sensitivity and higher variability. In this paper, we propose a novel design technique for integrating extended-gate OTFT ISFETs (OTFT EG-ISFETs) together with dual-gate OTFT multiplexers (MUXs) made in the same process. The achieved results show that our OTFT ISFET sensors are of the state of the art of the literature. Our microsystem architecture enables switching between the different ISFETs implemented in the chip. In the case of sensors with the same gain, we have a fault-tolerant architecture since we are able to replace the faulty sensor with a fault-free one on the chip. For a chip including sensors with different gains, an external processor can select the sensor with the required sensitivity.

Printed dual-gate organic thin film transistors and PMOS inverters on flexible substrates: role of top gate electrode

We report printed single and dual-gate organic thin film transistors (OTFTs) and p-channel metal-oxide-semiconductor (PMOS) inverters fabricated on 125 µm thick flexible polyethylene naphthalate substrate. All the electrodes (gate, source, and drain) are inkjet-printed, while the parylene dielectric is formed by chemical vapor deposition. A dispenser system is used to print the active channel material using a blend of 2,7-dihexyl-dithieno[2,3-d;2′,3′-d′]benzo [1,2-b;4,5-b′]dithiophene and polystyrene in tetralin solvent, which gives highest mobility of 0.43 cm2 V−1s−1. Dual-gate OTFTs are characterized by keeping the other gate electrode either in grounded or floating state. Floating gate electrode devices shows higher apparent mobility and current ratio due to additional capacitance of the parylene dielectric. PMOS inverter circuits are characterized in terms of gain, trip point and noise margin values calculated from the voltage transfer characteristics (VTC). Applied top gate voltage on the load OTFT control the conductivity or threshold voltage (V Th) of the bottom TFT and shift the trip point towards the middle of the VTC curve, and hence increase the noise margin.

Integrated complementary inverters and ring oscillators based on vertical-channel dual-base organic thin-film transistors

Lateral-channel dual-gate organic thin-film transistors have been used in pseudo complementary metal–oxide–semiconductor (CMOS) inverters to control switching voltage. However, their relatively long channel lengths, combined with the low charge carrier mobility of organic semiconductors, typically leads to slow inverter operation. Vertical-channel dual-gate organic thin-film transistors are a promising alternative because of their short channel lengths, but the lack of appropriate p- and n-type devices has limited the development of complementary inverter circuits. Here, we show that organic vertical n-channel permeable single- and dual-base transistors, and vertical p-channel permeable base transistors can be used to create integrated complementary inverters and ring oscillators. The vertical dual-base transistors enable switching voltage shift and gain enhancement. The inverters exhibit small switching time constants at 10 MHz, and the seven-stage complementary ring oscillators exhibit short signal propagation delays of 11 ns per stage at a supply voltage of 4 V.

Key aspects affecting the performances of high-K dielectrics based single-gate and dual-gate OTFTs

The single-gate (SG) and dual-gate (DG) organic thin-film transistors (OTFTs) performances have been analyzed by using high dielectric constant material. The dielectric and gate electrode material variation does the comparative study on SG (bottom-gate bottom-contact configuration) and DG-based OTFTs. Variation in thickness of the dielectric layer (step size 2) and channel length (step size 10) results in a deviation in the performance parameters like threshold voltage, mobility, ION/IOFF current ratio, subthreshold swing, trans-conductance, etc. Such variations in the performance of OTFT have been observed by using 2D numerical devices ATLAS simulator. Subsequently, it is analyzed that reduction in channel length from 50 µm to 10 µm leads to an increase in the drain current from −9.88 × 10−10 A to −5.8 × 10−9 A (in case of DG-OTFT) and from −9.84 × 10−11 A to −5.3 × 10−9 A (in case of SG-OTFT). Similarly, the reduction in dielectric layer thickness from 10 nm to 2 nm leads to an increase in the drive current/the current ratio from 3.9 × 1012 to 1.3 × 1013 (in case of SG-OTFT) and from 1.8 × 105 to 1.5 × 106 (in case of DG-OTFT). So achieving a better result, we switch to DG- OTFT compared to SG-OTFT, which would be helpful in various future applications like chemical sensors, circuits, RFIDs, etc.

Organic photodetector with built-in amplification for the detection of visible light with low optical power

We report on an organic-based photodetector that integrates a dual-gate organic thin-film transistor (DG-OTFT) with an organic photodiode (OPD) to produce a device with a high effective responsivity at low optical power and video-rate compatible response. In this device, the OPD operates in photovoltaic mode, instead of the commonly used photoconductive mode, to modulate one of the gate voltages of the DG-OTFT. Effective responsivity values of 10 A W−1 are measured at optical power values lower than 10 nW at 635 nm. Modeling of the operation of this new photodetector suggests that effective responsivity values up to 105 A W−1 can be achieved at optical powers of 1 nW using current printing technology and state-of-the-art organic semiconductors.

Enhanced Functionality of Dual-Gate Organic Transistors Based on Semiconducting/Insulating Polyblend-Induced Asymmetric Charge Modulation Layers.

Dual-gate organic thin-film transistors (DG-OTFTs) with enhanced functionality, including large current enhancement behavior, highly efficient threshold voltage controllability, and self-contained dual-mode logic gate features, are reported. These DG-OTFTs are based on a semiconducting/insulating polyblend-based active layer with asymmetric top and bottom charge modulation layers (atb-CMLs). The atb-CMLs are automatically generated through the preparation of multilayer stacks of phase-separated semiconducting poly(3-hexylthiophene) (P3HT):insulating poly(methylmethacrylate) (PMMA) polyblend layer, poly(vinylidene fluoride) (PVDF) layer, and cross-linked-poly(4-vinylphenol) (cPVP) layer. They consist of a thin PMMA bottom layer and an uneven-shaped PMMA:PVDF miscible mixture-based top layer. The presence of the polarizable insulating PMMA, PVDF, and PMMA:PVDF mixture regions causes the bottom and top CMLs to experience electrical polarization, which induces the dipole field to achieve efficient charge modulation functions in DG-OTFTs. Owing to the presence of atb-CMLs, the DG-OTFTs exhibit unprecedented electrical characteristics, such as the easy depletion of the bottom channel by the top gate potential. However, the top channel can work properly only when given a bottom gate potential (either positive or negative). Given these unusual electrical features, the design of the fundamental dual-mode logic gates (e.g., AND and OR gates) can be achieved with just one DG transistor. This finding opens an interesting direction for the preparation of DG-OTFTs with diverse operating modes and increasing functionality, thereby widening the application potential of such transistors.

Flexible inkjet-printed dual-gate organic thin film transistors and PMOS inverters: Noise margin control by top gate

Low operating voltage dual-gate p-type organic thin film transistors (OTFTs) and PMOS inverters have been fabricated on 125 μm-thick flexible polyethylene naphthalate (PEN) substrates by solution-processed techniques. Inkjet-printed silver electrodes are used for gate, source, and drain contacts while the active organic semiconducting material is printed by a dispenser system over parylene dielectric. Bottom channel, top channel, and dual-gate OTFTs separately display average charge carrier mobilities of 0.03, 0.11, and 0.37 cm 2 V −1 s −1 , respectively. Top-gate is used to independently tune the threshold voltage for bottom-gate OTFT and vice versa. Two PMOS inverters are fabricated with high gain and low supply voltage operation. Ideal symmetric voltage transfer characteristics with high noise margin are achieved by controlling the threshold voltage of the driver OTFT by top-gate bias for low supply voltage, V DD = −2.5 V. • Flexible low voltage dual-gate OTFTs are fabricated by inkjet printing technique. • Dual-gate OTFTs are characterized in bottom-, top-, and dual-gate mode. • V Th of bottom channel OTFT is linearly control by top gate and vice versa. • DLL and ZVLL, PMOS inverters are compared in terms of gain and noise margin. • Ideal PMOS inverters are achieved by controlling V Th of bottom OTFT by top gate.

Flexible PMOS Inverter and NOR Gate Using Inkjet-Printed Dual-Gate Organic Thin Film Transistors

We report the fabrication of low voltage dual-gate organic thin film transistors, and their possible applications for PMOS inverters and NOR logic gates, on $125~\mu \text{m}$ -thick flexible polyethylene naphthalate (PEN) substrates using solution-processed techniques. Source, drain, and gate electrodes are made by inkjet-printing, while active semiconductor is printed by a dispenser system over parylene dielectric. Bottom and top channel interfaces have been characterized by taking long drain current transients. Formation of stable top channel interface, with low trap density, is a reason for higher top channel current than bottom channel. Increase in drain current transients, and positive threshold voltage shift is attributed to the accumulation of extra positive charge carriers induced by slow polarization of the dipoles in the parylene dielectric.

Abnormal Back Channel Leakage Under Large Drain Voltage in Short Channel Organic Thin-Film Transistors

This study investigates short channel (length $ ) p-type organic thin-film transistor (OTFT) devices which exhibit off-state leakage in their ID–VG characteristics. This phenomenon is attributed to the fact that when a lower positive gate voltage is applied, gate voltage cannot control the back channel, causing back channel leakage. The behavior of back channel leakage is confirmed by the OTFT saturated-regime drain-current formula multiplied by channel length. For dual gate OTFT devices, a top gate voltage sweep and fixed different bottom gate voltages are applied, which indicates that the conduction path is distributed throughout the entire organic semiconductor (OSC) layer, and the back channel leakage can be suppressed by a positive bottom gate voltage. Finally, using dual gate sweeping for a dual gate OTFT device allows the top and bottom gate voltage to simultaneously control the front and back channels, causing a suppression of the back channel leakage, an improvement in subthreshold swing (SS) from 420 to 200 (mV/decade) and an on current increase from $\textsf {7.8}\times \textsf {10}^{-\textsf {8}}$ to $\textsf {3.3}\times \textsf {10}^{-\textsf {7}}$ A at VG-Vsub-threshold = −8 V for the W/L $=50/20~\mu \text{m}$ device.

TCAD SIMULATION AND PERFORMANCE ANALYSIS OF SINGLE AND DUAL GATE OTFTs

This paper presents finite element-based numerical simulation and performance analysis of dual and single gate pentacene-based organic thin film transistors (OTFTs) using technology computer-aided design (TCAD) tools. Electrical characteristics of the devices have been simulated using 2D numerical device simulation software ATLAS™ from Silvaco International. Also, device parameters like threshold voltage, mobility, transconductance, subthreshold swing and current on/off ratio of the single and dual gate OTFTs have been extracted and compared.

Bistaggered Contact Geometry for Symmetric Dual-Gate Organic TFTs

This transaction proposes a symmetric bistaggered dual-gate organic thin-film transistor (TFT) to minimize the difference between the top and bottom channel current characteristics and demonstrates it through experiment and 2-D simulation. In dual-gate organic TFTs, asymmetric top and bottom channel currents are mainly a result of their asymmetric contact geometry. To address this geometric limitation, the contact electrodes were sandwiched between the two organic semiconductor layers to be placed in a staggered position to both top and bottom gates. Two-way current crowding at the bistaggered contact electrodes leads to high-charge injection efficiency in both channels.

Charge Carrier Distribution in Low-Voltage Dual-Gate Organic Thin-Film Transistors

Dual-gate organic thin-film transistors (DGOTFTs), which exhibit better electrical properties, in terms of on-current and subthreshold slope than those of single-gate organic thin-film transistors (OTFTs) are promising devices for high-performance and robust organic electronics. Electrical behaviors of high-voltage (>10 V) DGOTFTs have been studied: however, the performance analysis in low-voltage DGOTFTs has not been reported because fabrication of low-voltage DGOTFTs is generally challenging. In this study, we successfully fabricated low-voltage (<5 V) DGOTFTs by employing thin parylene film as gate dielectrics and visualized the charge carrier distributions in low-voltage DGOTFTs by a simulation that is based on finite element method (FEM). The simulation results indicated that the dual-gate system produces a dual-channel and has excellent control of charge carrier density in the organic semiconducting layer, which leads to the better switching characteristics than the single-gate devices.

Impact of gate coupling and misalignment on performance of double-gate organic thin film transistors

This paper proposes a numerical simulation of the dual-gate organic thin film transistors (DG-OTFTs). It is revealed that electrically separable double-gate architecture is able to dynamically control the threshold voltage by the coupling of the top/bottom gates. We also observe that the device characteristics are sensitive to the misalignment and the moving direction between top/bottom gates. A significant change to the driving ability and threshold voltage is found while misalignment exists. As the misalignment is larger, the driving-current reduces and threshold voltage increases quickly. Also the degradation is severe while the mismatch is moved to drain and relaxed with large channel length.

Static and dynamic characteristics of dual gate organic TFT based NAND and NOR circuits

This research paper analyzes the static and dynamic behavior of dual-gate organic thin film transistors (DG-OTFTs) based universal logic gates using the Atlas 2-D numerical device simulator. The electrical characteristics and performance parameters of pentacene based DG-OTFT is evaluated and verified with respect to the reported experimental results. The NAND and NOR logic gate circuits are realized using $$p$$ p -type designs in diode-load logic (DLL) and zero- $$V_{gs}$$ V g s -load logic (ZVLL). The results show that the logic functions in ZVLL configuration outperforms the DLL ones mainly in terms of noise margin, gain and voltage swing; however, there is a trade-off in terms of speed. The ZVLL NAND gate demonstrates an increment of 16 and 32 % in voltage swing and noise margin, respectively in comparison to the DLL one. Besides this, the gain also increases by 1.5 times in ZVLL mode. On the contrary, the DLL configuration demonstrates a significant reduction of 64 % in the propagation delay in comparison to the ZVLL. Similarly, NOR gate shows an increment of 24 and 30 % in voltage swing and noise margin, respectively under ZVLL configuration. However, the propagation delay for DLL NOR configuration is one-fourth of that of its ZVLL counterpart.

Single and dual gate OTFT based robust organic digital design

This paper analyzes and compares the performance of the single gate (SG) and dual gate (DG) organic thin film transistors (OTFTs) based inverter circuits. The DG-OTFT device performs better than SG-OTFT mainly in terms of mobility, on–off current ratio and sub-threshold slope. The mobility of DG device is almost five times higher than the SG, while, an increase of 74% in on–off current ratio and a decrease of 41% in sub-threshold slope are observed. Two different configurations of inverter circuits i.e. diode-load logic (DLL) and zero-Vgs-load logic (ZVLL) are studied. The static and dynamic behaviors of the p-type DLL and ZVLL inverters using SG and DG organic transistors are observed. The DG-OTFT improves gain and noise margins for both DLL and ZVLL inverter circuits. Using DG device, propagation delay reduces by 59% for DLL and 42% for ZVLL as compared to SG OTFT based configurations. Moreover, fixed back gate bias technique further enhances the noise margin and gain by 8% and 18% for DLL and 19% and 26% for ZVLL configurations, respectively. Finally, bootstrapping technique is also applied to the dual gate inverters that further boosts the noise margin and gain for DLL and ZVLL configurations.

High mobility organic thin film transistor and efficient photovoltaic devices using versatile donor–acceptor polymer semiconductor by molecular design

In this work, we report a novel donor–acceptor based solution processable low band gap polymer semiconductor, PDPP–TNT, synthesized via Suzuki coupling using condensed diketopyrrolopyrrole (DPP) as an acceptor moiety with a fused naphthalene donor building block in the polymer backbone. This polymer exhibits p-channel charge transport characteristics when used as the active semiconductor in organic thin-film transistor (OTFT) devices. The hole mobilities of 0.65 cm2 V−1s−1 and 0.98 cm2 V−1s−1 are achieved respectively in bottom gate and dual gate OTFT devices with on/off ratios in the range of 105 to 107. Additionally, due to its appropriate HOMO (5.29 eV) energy level and optimum optical band gap (1.50 eV), PDPP–TNT is a promising candidate for organic photovoltaic (OPV) applications. When this polymer semiconductor is used as a donor and PC71BM as an acceptor in OPV devices, high power conversion efficiencies (PCE) of 4.7% are obtained. Such high mobility values in OTFTs and high PCE in OPV make PDPP–TNT a very promising polymer semiconductor for a wide range of applications in organic electronics.

A Fully Integrated $\Delta \Sigma$ ADC in Organic Thin-Film Transistor Technology on Flexible Plastic Foil

In this work we present a fully integrated first order continuous-time ΔΣ ADC made in a pentacene-based dual-gate organic thin-film transistor technology on flexible plastic foil. The ADC achieves a precision of 26.5 dB at a clock speed of 500 Hz and draws 100 μA from a 15 V power supply. As sub-blocks of the ADC, we also present a Vt -insensitive single-stage differential amplifier with 10 kHz GBW, a 3-stage operational amplifier, an integrator, a comparator and a level shifter. The circuits are designed following a strict Vt -insensitive design strategy and use high-pass filters for offset cancellation. The active area is 13 × 20 mm2.

Dual-gate field-effect transistors of octathio[8]circulene thin-films with ionic liquid and SiO2 gate dielectrics

Dual-gate organic thin-film transistors (OTFTs) of octathio[8]circulene (1) with ionic liquid and SiO2 gate dielectrics lead to good transistor performance with a high on/off ratio (∼105), a low threshold voltage (∼−5 V), a low subthreshold slope (∼150 mV/decade), and low power operation, thus surpassing the performance of the single-gate OTFTs of 1. This operation is a promising method for improving the carrier concentrations in OTFTs and for realizing high-performance OTFTs.