Flexible PMOS Inverter and NOR Gate Using Inkjet-Printed Dual-Gate Organic Thin Film Transistors

Abstract

We report the fabrication of low voltage dual-gate organic thin film transistors, and their possible applications for PMOS inverters and NOR logic gates, on $125~\mu \text{m}$ -thick flexible polyethylene naphthalate (PEN) substrates using solution-processed techniques. Source, drain, and gate electrodes are made by inkjet-printing, while active semiconductor is printed by a dispenser system over parylene dielectric. Bottom and top channel interfaces have been characterized by taking long drain current transients. Formation of stable top channel interface, with low trap density, is a reason for higher top channel current than bottom channel. Increase in drain current transients, and positive threshold voltage shift is attributed to the accumulation of extra positive charge carriers induced by slow polarization of the dipoles in the parylene dielectric.