Static and dynamic characteristics of dual gate organic TFT based NAND and NOR circuits

Abstract

This research paper analyzes the static and dynamic behavior of dual-gate organic thin film transistors (DG-OTFTs) based universal logic gates using the Atlas 2-D numerical device simulator. The electrical characteristics and performance parameters of pentacene based DG-OTFT is evaluated and verified with respect to the reported experimental results. The NAND and NOR logic gate circuits are realized using $$p$$ p -type designs in diode-load logic (DLL) and zero- $$V_{gs}$$ V g s -load logic (ZVLL). The results show that the logic functions in ZVLL configuration outperforms the DLL ones mainly in terms of noise margin, gain and voltage swing; however, there is a trade-off in terms of speed. The ZVLL NAND gate demonstrates an increment of 16 and 32 % in voltage swing and noise margin, respectively in comparison to the DLL one. Besides this, the gain also increases by 1.5 times in ZVLL mode. On the contrary, the DLL configuration demonstrates a significant reduction of 64 % in the propagation delay in comparison to the ZVLL. Similarly, NOR gate shows an increment of 24 and 30 % in voltage swing and noise margin, respectively under ZVLL configuration. However, the propagation delay for DLL NOR configuration is one-fourth of that of its ZVLL counterpart.