Dual Damascene Interconnects Research Articles

Copper voids improvement for the copper dual damascene interconnection process

The mechanism of copper (Cu) voids formation from electro-chemical plating (ECP) followed by Cu chemical mechanical polishing (CMP) are studied in Cu dual-damascene interconnection. The formation of Cu voids at metal lines is the main problem that causes not only the failure of via-induced metal-island corrosion but also yield loss. The galvanic theory and Cu lifting mechanism are proposed to explain the dependence of Cu-void performance on the Cu grain size and the benzotriazole (BTA, C 6H 5N 3) flow rates. In the integration process of Cu interconnects, it is found that the smaller Cu grain size in ECP conditions and less BTA flow rate in CMP processes cannot only reduce the number of Cu voids but also improve the wafer yield.

Improving Reliability of Copper Dual-Damascene Interconnects by Impurity Doping and Interface Strengthening

Electromigration (EM)-derived void nucleation and growth in 65-nm-node dual-damascene interconnects were investigated, and the effects of impurity doping as well as copper adhesion strength to a capping-dielectric layer (CAP) are clarified. It is found that surface-reductive treatment of the copper line improves its adhesion to the SiCN-CAP, elongating the incubation time of voiding at the via bottom. An aluminum doping is effective in suppressing both the void nucleation and growth. Consequently, an aluminum-doped copper alloy with the strong copper/CAP interface improves the EM lifetime by 50 times compared to that of a conventional pure copper. These results clearly indicate that blocking migration paths of vacancies through both grain boundaries and the copper/CAP interface is essential in improving the EM reliability.

Electromigration characteristics in dual-damascene copper interconnects by difference of via structures

In order to improve the interconnect performance, copper has been used as the interconnect material instead of aluminum. One of the advantages of using copper interconnects instead of aluminum is better electromigration (EM) performance and lower resistance for ultralarge-scale integrated (ULSI) circuits. Dual-damascene processes use different approaches at the via bottom for lowering the via resistance. In this study, the effect of a Ta/TaN diffusion barrier on the reliability and on the electrical performance of copper dual-damascene interconnects was investigated. A higher EM performance in copper dual-damascene structures was obtained in barrier contact via (BCV) interconnect structures with a Ta/TaN barrier layer, while a lower EM performance was observed in direct contact via (DCV) interconnect structures with a bottomless process, although DCV structures had lower via resistance compared to BCV structures. The EM failures in BCV interconnect structures were formed at the via, while those in DCV interconnect structures were formed in the copper line. The existence of a barrier layer at the via bottom was related to the difference of EM failure modes. It was confirmed that the difference in EM characteristics was explained to be due to the fact that the barrier layer at the via bottom enhanced the back stress in the copper line.

Effects of microvoids on the linewidth dependence of electromigration failure of dual-damascene copper interconnects

The electromigration lifetime of dual-damascene Cu interconnects was found to significantly decrease with increasing linewidth, for linewidths ranging between 0.2 and 2.25μm. Voids were also found to preexist in these lines. When void nucleation is required for failure, the electromigration reliability is generally found to be at most weakly dependent on the linewidth. In contrast, the current study suggests that growth, drift, and accumulation of existing voids lead to the observed strong linewidth dependence.

A-SiC:H low- k deposition as copper diffusion barrier layer in advanced microelectronic interconnections

This study deals with the deposition of a new a-SiC:H material as barrier layer against copper diffusion in dual damascene interconnections for microelectronics. Indeed, new low- k dielectric barriers ( k < 4) must be introduced into the future technologies allowing chip miniaturization and performances improvement. In this work, films were deposited on silicon wafers by RF-PECVD, with trimethylsilane and toluene as gas precursors and He as carrier gas. One of the main challenges of this work was to correlate the presence of phenyl rings in the film with the material dielectric constant. It is shown that soft plasma conditions such as high pressure, low dilution, high toluene flow rate, low power, and low temperature were necessary to incorporate phenyl rings in the film. These soft plasma conditions also allow increasing the total amount of carbon in the film. The film dielectric constant can be reduced from 4.5 to 3.1 depending on the carbon content incorporated and the correlation with the presence of phenyl rings in the film is discussed.

Surface Control of Bottom Electrode in Ultra-Thin SiN Metal–Insulator–Metal Decoupling Capacitors for High Speed Processors

Highly reliable metal–insulator–metal (MIM) capacitor with ultra-thin SiN dielectrics is developed on the surface-controlled bottom electrode in nanometer-scales. Coverage of the TiN bottom electrode with a Ta thin layer achieves smooth surface. In addition, this electrode structure exhibits excellent etching controllability even for the MIM with the ultra-thin SiN dielectrics. The smooth surface of the Ta/TiN stacked electrode improves the dielectric characteristics such as leakage, breakdown and time-dependent dielectric breakdown (TDDB) reliability in the MIM capacitors, integrated into Cu dual-damascene interconnects (DDIs). As a result, the SiN-MIM with the Ta/TiN bottom electrode achieves high capacitance of 7 fF/µm2 as well as high reliabilities, which are 20% higher breakdown field and 6000 times longer TDDB lifetime than that without Ta-insertion. These values guarantee the high performance operation for more than 10 years under the environment at 85 °C.

Reliability computer-aided design tool for full-chip electromigration analysis and comparison with different interconnect metallizations

We have developed a set of methodologies for thermal aware circuit-level reliability analysis with either Al or Cu metallization in a circuit layout and implemented it in a public domain reliability CAD tool, SysRel. SysRel utilizes a hierarchical reliability analysis flow, with interconnect trees treated as the fundamental reliability unit, that sufficiently captures the differences in electromigration failure between Al and Cu metallizations. Under similar test conditions, the electromigration reliability of Al and Cu interconnect trees demonstrates significant differences because of the differences in interconnect architectural schemes. Using the best estimates of material parameters and an analytical model, we present a detail comparison of electromigration reliability of a sample test-structure as well as of actual circuit layouts with Al and Cu dual-damascene interconnect systems. We also demonstrate fast thermal-analysis in SysRel for circuit performance driven chip-level reliability assessment.

Analytical modeling of reservoir effect on electromigration in Cu interconnects

Electromigration (EM) in Cu dual-damascene interconnects with extensions (also described as overhangs or reservoirs) ranging from 0 to 120 nm in the upper metal (M2) was investigated by an analytical model considering the work of electron wind and surface/interface energy. It was found that there exists a critical extension length beyond which increasing extension lengths ceases to prolong electromigration lifetimes. The critical extension length is a function of void size and electrical field gradient. The analytical model agrees very well with existing experimental results. Some design guidelines for electromigration-resistant circuits could be generated by the model.

Robust Cu Dual Damascene Interconnects With Porous SiOCH Films Fabricated by Low-Damage Multi-Hard-Mask Etching Technology

Low-damage hard-mask (HM) plasma-etching technology for porous SiOCH film (k=2.6) has been developed for robust 65-nm-node Cu dual damascene interconnects (DDIs). No damage is introduced by fluorocarbon plasma etching irrespective of whether rigid (k=2.9) or porous (k=2.6) SiOCH films are used, due to the protective CF-polymer layer deposited on the etched sidewall. The etching selectivity of the SiOCH films to the inorganic HMs is kept high by controlling the radical ratio of carbon relative to oxygen in the etching plasma gas. However, oxidation damage penetrates the films from the sidewalls due to the O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> plasma used for photoresist ashing. This damage is increased by the porous structure. As a result, we developed a via-first multi-hard-mask process for the DD structure in porous SiOCH film with no exposure to O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> -ashing plasma, and we controlled the via-taper angle by RF bias during etching. We fabricated robust Cu DDIs with tapered vias in porous SiOCH film that can be applied to 65-nm-node ULSIs and beyond

Highly reliable copper dual-damascene interconnects with self-formed MnSi/sub x/O/sub y/ barrier Layer

Copper (Cu) dual-damascene interconnects with a self-formed MnSi <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">y</sub> barrier layer were successfully fabricated. Transmission electron microscopy shows that approximately 2-nm thick and continuous MnSi <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">y</sub> layer was formed at the interface of Cu and dielectric SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> , and that no barrier was formed at the via bottom because no oxygen was at the via bottom during annealing. No leakage-current increase was observed, and electron energy loss analysis shows that no Cu was in SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> , suggesting that MnSi <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">x</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">y</sub> layer has sufficient barrier properties for Cu, and that the concept of self-forming barrier process works in Cu dual-damascene interconnects. Via chain yield of more than 90% and 50% reduction in via resistance were obtained as compared with physical vapor deposited tantalum barrier, because there is no barrier at the via bottom. In addition, no failure in the stress-induced voiding measurement was found even after a 1600-h testing. No failure in electromigration (EM) testing was found, as the electron flow is from the lower level interconnects through via up to upper level interconnects even after 1000-h testing. At least, four times EM lifetime improvement was obtained in the case of electron flow from upper level interconnect through via down to lower level interconnects. Significant EM lifetime improvement is due to no flux divergence site at the via bottom, resulting from there being no bottom barrier at the via

Reservoir effect and the role of low current density regions on electromigration lifetimes in copper interconnects

Electromigration (EM) in copper dual-damascene interconnects with extensions(also described as overhang regions or reservoirs) in the upper metal (M2) were investigated. It was found that as the extension length increases from 0 to 60 nm, the median-time-to-failure increased from 50 to 140 h, representing a ∼200% improvement in lifetimes. However, further increment of the extension length from 60 to 120 nm did not result in any significant improvement in EM lifetimes. Based on calculations of current densities in the reservoir regions and recently reported nucleation, void movement, and agglomeration-based EM phenomena, it is proposed that there is a critical extension length beyond which increasing extension lengths will not lead to longer EM lifetimes.

Noncontact electrical metrology of Cu/low-k interconnect for semiconductor production wafers

We have demonstrated a technique capable of in-line measurement of dielectric constant of low-k interconnect films on patterned wafers utilizing a test key of ∼50×50μm2 in size. The test key consists of a low-k film backed by a Cu grid with &amp;gt;50% metal pattern density and &amp;lt;0.25μm pitch, which is fully compatible with the existing dual-damascene interconnect manufacturing processes. The technique is based on a near-field scanned microwave probe and is noncontact, noninvasive, and requires no electrical contact to or grounding of the wafer under test. It yields &amp;lt;0.3% precision and ±2% accuracy for the film dielectric constant.

Adhesion Studies of Ta ∕ Low-k (Black Diamond) Interface using Thermocompressive Wafer Bonding and Four-Point Bend

The four-point bend test is used to quantitatively determine the adhesion energy of the (Black Diamond) interface, a technologically important interface found in a dual-damascene interconnection system. The samples containing the interface of interest were prepared by wafer-level Cu thermocompression bonding. By bonding the Cu wafers at for at without any prior prebond surface clean helps to form a moderately weaker bonding interface, which deflects the vertical precrack to the direction parallel to the interface of interest. The crack then seeks out a new weak path for further growth, and this mode mixity ensures that it kinks downward to the multilayer containing the interface. Focused-ion beam scanning electron microscopy, cross-sectional scanning electron microscopy, and Auger analysis are used to evaluate the failure interfaces.

Failure Mechanism of Electromigration in Via Sidewall for Copper Dual Damascene Interconnection

We have studied the effects of step coverage of TaN diffusion barrier layer on Cu electromigration (EM) in detail and found that the EM lifetime strongly depends on the step coverage of via sidewall thickness. We conclude that the EM failures are caused by mechanisms such as unbalanced thermal stress, thermal expansion between Cu and TaN, and surface morphology of TaN including surface roughness and grain sizes. These factors were investigated and evaluated systematically through transmission electron microscopy, field emission scanning electron microscopy, and atomic force microscopy. Furthermore, we also address the enhancement of step coverage to examine Cu EM performance by performing a lifetime experiment, and suggest that the step coverage of TaN barrier becomes an important process integration subject for sub- and beyond technologies.

Copper Resistivity in Electrodeposited Dual Damascene Interconnects - An Integrated Circuit Perspective

not Available.

A direct measurement of electromigration induced drift velocity in Cu dual damascene interconnects

A dual damascene structure with an additional 25 nm Ta diffusion barrier embedded into the upper Cu layer was fabricated to measure the drift velocity of electromigration. The embedded diffusion barrier layer successfully confined void growth into a long and regular shape between the SiN layer and embedded Ta layer. Edge depletion was observed to initiate from the cathode end and elongate into a long and regular shape due to the confinement of the intermediate Ta diffusion barrier layer. With this test structure, electromigration induced drift displacement can be accurately measured with a linear dependence on time. Measurement was conducted at a series of temperatures to obtain the Cu/capping interface diffusion controlled activation energy.

Copper Interconnect Electromigration Behavior in Various Structures and Precise Bimodal Fitting

Copper interconnect electromigration (EM) was examined in various structures and three low-k materials (k=2.65–3.6) using advanced back-end-of-line (BEOL) technology. Various structures for testing were designed to identify the EM failure modes, and extensive failure analysis was carried out to reveal failure in the test structures. A strong current dependence of the electromigration lifetime in three-level via-terminated metal lines was shown. Moreover, different processing approaches lead to different EM behaviors and related failure modes. The weak links of the interconnect system were identified by evaluating various test structures. Multimodality in the electromigration behavior of Cu dual-damascene interconnects was studied. Both superposition and weak-link models were used for the statistical determination of lifetimes of each failure model (statistical method). Results correlated to the lifetimes of the respective failure models physically identified according to resistance time evolution behavior (physical method). A good agreement was achieved. The activation energies of failure modes were calculated. Results of this study suggest that the interface of Cu interconnects is the key factor in EM performance.

Confinement of electromigration induced void propagation in Cu interconnect by a buried Ta diffusion barrier layer

Direct observation, by means of in situ scanning electron microscopy, of void heterogeneous nucleation and migration controlled electromigration failure mechanism in Cu dual damascene interconnect structures has been recently reported [A. V. Vairagar, S. G. Mhaisalkar, A. Krishnamoorthy, K. N. Tu, A. M. Gusak, M. A. Meyer, and E. Zschech, Appl. Phys. Lett. 85, 2502 (2004)] In the present study, a dual damascene structure with an additional 25nm Ta diffusion barrier embedded into the upper Cu layer was fabricated. This thin layer of diffusion barrier blocked voids from propagating into the via, thus eliminating the previously reported failure mechanism. With this structure, a lifetime improvement of at least 40 times was achieved. Analysis on failed samples suggested that failures in samples with the embedded Ta barrier layer occurred at the bottom of the via, which were caused by void migration along the bottom of the Cu lines.

Effect of Cu3Sn coatings on electromigration lifetime improvement of Cu dual-damascene interconnects

A 20 nm thick Cu3Sn intermetallic compound overlayer on Cu interconnect surfaces was found to effectively block dominant surface diffusion paths, thus resulting in close to one order of magnitude improvement in electromigration lifetimes. This improvement may be explained on the basis of the terrace-ledge-kink model in which the supply of Cu adatoms by the dissociation of atoms from the kinks on the Cu surface steps is hindered by a stronger chemical binding of Sn atoms to the kink sites. The mode of electromigration failures seem to have changed from surface diffusion-induced void formation at the cathode via corner to interfacial and grain-boundary diffusion-induced void formation in the interconnect line.

The influence of temperature and dielectric materials on stress induced voiding in Cu dual damascene interconnects

In this work, package level stress migration test of Cu dual-damascene interconnects in via-line structures was performed. The effects of stressing temperature and dielectric materials on SIV behavior were investigated. The via-line structures were studied at temperatures ranging from 150 to 250 °C, with highest failure rate being detected at 200 °C. In comparing stress migration data on carbon doped oxide (CDO) with undoped silica glass (USG), a difference of two orders of magnitude was detected in the rate of change of resistance. About 40% of the CDO samples showed open circuit failures after a 1344-h test, whereas the maximum resistance change in the USG samples was only 10%. Failure analysis indicated that failures in both CDO and USG were very similar in nature. In both cases, voids formed symmetrically at the bottom of the via, showing that the integrity of the Ta barrier in the via bottom area was of significant influence to stress induced voiding. Finite element analysis (FEA) indicated that the driving force for void growth, the gradient of hydrostatic stress, at via bottom in CDO structure is 30% higher than the one in USG. Besides the stress gradient, other factors that could affect SIV behaviour are the back stress and interface adhesion. Similar to the case of electromigration, back stress might be generated during stress migration, provided that the interface between the Cu line and the surrounding dielectric material is strong. Back stress reverses the trend of migration of atoms. Discussion and comparison of all these factors are made between the two types of dielectrics in order to explain the observed higher failure rate of stress-induced-voiding in CDO structures.