Dual Damascene Interconnects Research Articles

Plasma-Etching Technology With In Situ Etched-Surface Modification for Highly Reliable Low-<tex>$ k$</tex>/Cu Dual Damascene Interconnects

The plasma-etching technology presented in this paper is for fabricating highly reliable Cu dual damascene interconnects (DDI) with organic low-k film through modification of the in situ etched surface during low-k etching. Nitrogen-based plasma with oxygen and high-molecular-weight fluorocarbon gas (C>2) chemically modifies the sidewall surface of the etched low-k film, changing it into the carbon nitride with fluorocarbon-polymer passivation from the etching gas. After wet cleaning, the fluorocarbon-polymer is removed selectively, leaving a carbon nitride modified layer (CNL) on the sidewall. The CNL has been found to suppress Cu diffusion into the low-k film. A stacked barrier structure of conventional barrier metal and CNL is expected to have high tolerance to Cu diffusion. Combining a dual-hard-mask etching sequence with the CNL modification, Cu DDIs with organic low-k film were fabricated with high yield.

The effect of line width on stress-induced voiding in Cu dual damascene interconnects

The influence of M1 (lower level Cu) line width on stress-induced voiding (SIV) behavior of copper dual damascene interconnects was investigated by stress migration test at 200 °C and finite element analysis (FEA). M1 line width under study ranged from 200 nm to 1000 nm, whereas the M2 line width was fixed to be 3 μm. The normalized change in resistance indicated that the via-line structures with larger M1 line width were more susceptible to SIV. Failure analysis utilizing focus ion beam (FIB) showed that voids were formed in the via bottom region for samples with M1 line width less than 280 nm. However, voids were found at the Si 3N 4/M1 Cu interface near the via bottom if M1 line width is larger than 280 nm. To further understand the underlying physics of SIV, three dimensional finite element models were built to simulate the hydrostatic stress distribution in the via-line structures. It was found that the stress gradient in the length direction, grad σ l, was not sensitive to M1 line width, however, the stress gradient in the line width direction, grad σ w, was found to increase with M1 line widths. It is thus proposed that in addition to the active diffusion volume, it is the grad σ w that further favors the migration of voids (or vacancies) along the Si 3N 4/M1 Cu interface and subsequent accumulation of the voids near the via bottom leading to a much higher resistance change at larger M1 widths.

Effect of inter-level dielectrics on electromigration in damascene copper interconnect

The impact of dielectric materials on the reliability of advanced copper (Cu) interconnect is of growing importance. The effect of barrier dielectrics and low- k materials of Inter-Level Dielectric (ILD) on the electromigration (EM) in the line and via-line structure of dual-damascene Cu interconnects was analyzed. The resulting electromigration behavior can then be attributed to Cu barrier layer or low- k dielectrics, depending on the test structure. The SiN barrier layer showed a better electromigration endurance compared to SiC barrier layer for narrow Cu line structure. We had also observed that the carbon-doped oxide (CDO) low- k samples had a higher drift velocity, which results in less electromigration endurance on the via-line structure compared to fluorosilicate glass (FSG).

Temporary extrusion failures in accelerated lifetime tests of copper interconnects

A novel electromigration mode was detected in 0.13-/spl mu/m technology, copper dual damascene interconnects. Extrusions formed between the test lead and neighboring monitor lines, resulting in short-circuit However, many of these extrusions were short lived, shrinking within a period of a minute to an hour. These phenomena indicated that a temporary failure existed in accelerated copper electromigration tests in addition to the traditional permanent or hard failure. These soft failures would be missed unless short sampling intervals (less than a minute) and continuous monitoring of the leakage current between test metal lines and neighboring circuits were carried out. Consistent with our experimental results, physical modeling suggested that capillary forces were able to rupture a long and narrow extrusion and the electric field across the extrusion could accelerate this process.

Reservoir effect on electromigration mechanisms in dual-damascene Cu interconnect structures

Reservoir effect in dual-damascene Cu interconnect structures caused by electromigration was studied by in situ secondary electron microscopy (SEM). Electromigration-induced void nucleation and apparent void movement in opposite direction to electron flow along the Cu/SiN x interface was found to be responsible for the observed reservoir effect. The observed void evolutions seem to be contrary to current understanding of reservoir effect based on maximum tensile stress developed at the cathode via and on current gradient induced vacancy flux. The influence of the observed reservoir effect on electromigration mechanisms is discussed in detail.

200 mm wafer-scale substrate transfer of 0.13μmCu∕low-k (Black Diamond™) dual-damascene interconnection to glass substrates

We report a low-temperature (350 °C) pulsed-voltage anodic bonding followed by grind/etch-back method for 200 mm wafer-scale substrate transfer of 0.13μmCu∕low-k (Black Diamond™) dual-damascene interconnection to glass substrates. Standard back-end-of-line (BEOL) 3kÅSiN∕3kÅ undoped Si glass passivating films were used as buffer layers between donor wafer and glass wafer to facilitate the bonding. We demonstrate removal of the silicon bulk layer to leave behind a transparent (∼1.25μm thick) 0.13μm BEOL circuit on a 1-mm-thick glass wafer. The quality of the mechanical and electrical integrity of the deep submicron BEOL circuit is confirmed by focused ion beam-scanning electron microscopy microscopy and I-V characterization on via chain test structures. This technique has potential applications for bioelectronics and optoelectronics integration schemes.

Current crowding effect on copper dual damascene via bottom failure for ULSI applications

Reliability of interconnect via is increasing an important issue in submicron technology. Electromigration experiments are performed on line/via structures in two level Cu dual damascene interconnection system and it is found that wide line/via fails earlier than the narrow line/via. Atomic flux divergence based finite element analyses is performed and stress-migration is found to be important in the failure rate behavior observed. Semi-classical width dependence Black's equation together with the finite element analysis revealed that the difference in the time to failure is due to the much larger average current density along the interface between the line and via for the wide line/via structure, and good agreement is obtained between the simulation and experimental results.

Process improvement of 0.13 μm Cu/Low K (Black Diamond TM) dual damascene interconnection

Once fab develops a reliable integration scheme, the next step of process improvement and yield enhancement is very important for semiconductor industry, especially for the 0.13 μm Cu/Low K (Black Diamond TM) dual damascene interconnection. In this paper, we discuss the process integration issues of the 0.13 μm Cu/Low K (Black Diamond TM) dual damascene integration. Solutions to the issues were explored and reported. Resist poisoning issue was solved by modifying photoresist and planarizing bottom-anti-reflective-coating (BARC) scheme. As a result there is an increase of 20% electrical yield. The impact of via etch time on interface of via bottom was studied and etch time was optimized for the best electrical performance of via chains. One of major targets of the 0.13 μm Cu/Low K (Black Diamond TM) dual damascene integration is the reliability improvement. It was observed that Cu cap etch results in different via chain profiles. Good profile of via chain is achieved after optimizing of Cu cap etch and via etch. The failure open rate of via chain and the highest dielectric breakdown field were also reported. The impacts of dual damascene cleaning on the reliability of the 0.13 μm Cu/Low K (Black Diamond TM) dual damascene interconnection was studied with splits between batch process and single wafer cleaning. On the whole, we successfully integrated 0.13 μm Cu/Low K (Black Diamond TM) dual damascene interconnection with good electrical and reliability performance after process improvement of patterning, via/Cu cap etch and dual damascene cleaning.

Effects of the Metallurgical Properties of Upper Cu Film on Stress-Induced Voiding (SIV) in Cu Dual-Damascene Interconnects

Stress-induced voiding (SIV) is a serious problem in Cu dual-damascene interconnects (DDIs). The stress gradient under vias is the driving force of vacancy diffusion and void generation, therefore stress control in Cu-DDI is an important factor for suppressing SIV. In this study, the stress effect of upper Cu film on SIV in lower Cu lines is investigated, and the stress distribution in Cu-DDI is analyzed by finite element analysis. It is found that SIV in the lower Cu lines is strongly affected not only by the width of lower lines but also by the metallurgical properties of the Cu film in upper metals. Suppression of tensile stress in the via of the upper Cu film decreases the stress gradient in the lower line around the via, and eventually, the driving force of vacancy diffusion to the via bottom. Control of the metallurgical properties to suppress Cu creep during annealing is a key factor for decreasing SIV in lower Cu lines. High-temperature deposition of Cu film with a small coefficient of thermal expansion (CTE) is a solution to suppressing SIV failure in Cu-DDIs.

The Effect of Immersion Sn coating on the Electromigration Failure Mechanism and Lifetimes of Cu Dual Damascene Interconnects

AbstractIn sub-micron dual damascene Cu interconnects, electromigration occurs mainly along the interfaces between Cu and dielectric cap layer. Many reports have shown that the interface of Cu/dielectric cap is the dominant diffusion path. In-situ electromigration experiments were carried out recently by A. V. Vairagar etal [APPL. PHYS. LETT., 85, 2502 (2004)] to investigate the electromigration failure mechanisms in the upper and lower layers in dualdamascene Cu test structures. It was found that electromigration-induced void first nucleates at locations which are far from the cathode, then moves along the Cu/dielectric cap interface in opposite direction of electron flow, and eventually causes void agglomeration at the via in the cathode end to open the interconnect. In the present study, immersion Sn (20 nm) was employed after CMP and before SiN deposition. All the samples, with a line-width of 0.28 um, were assessed by package level electromigration tests at 300°C under a current density of 3.6MA/cm2. We found that immersion Sn surface treatment effectively introduced the Cu-Sn bonding to the Cu/dielectric interface and has influenced electromigration along the Cu/dielectric interfaces. Failure analysis shows that the samples with these Sn processes have a median-time-to-failure almost 1 order of magnitude larger than the control samples. A careful characterization utilizing FIB and SEM cross-sectional images shows that the failure mechanism has changed due to the Sn surface treatments. After electromigration-induced void nucleation, its movement is blocked by the strong Cu-Sn bonding so that its growth is localized and occurs along grain boundaries. With the increased impedance to surface diffusion, failure analysis seems to indicate that grain boundary diffusion now participates in the void movement and growth, which is proposed to be the reason for the increased lifetime.

Copper interconnect electromigration behaviors in various structures and lifetime improvement by cap/dielectric interface treatment

Copper interconnect electromigration performance was examined in various structures and three low- k materials ( k = 2.65–3.6) using advanced BEOL technology. Strong current dependence effect on electromigration lifetime in three levels via terminated metal lines structure was shown. Moreover, different process approach will lead to different EM behavior and related failure mode. Multi-modality electromigration behavior of Cu dual damascene interconnects were studied. Both Superposition and Weak-Link models were used for statistical determination of lifetimes of each failure models (Statistical method). Results were correlated to the lifetimes of respective failure models physically identified according to resistance time evolution behaviors (Physical method). Good agreement was achieved. Various testing structures are designed to identify the EM failure modes. Extensive failure analysis was carried out to understand the failure phenomena of various test structures. The activation energies of failure modes were calculated. The weak links of interconnect system were also identified. A significant improvement of electromigration (EM) lifetime is achieved by modification of the pre-clean step before cap-layer deposition and by changing Cu cap/dielectric materials. A possible mechanism for EM lifetime enhancement was proposed. Cu-silicide formation before cap-layer deposition and adhesion of Cu/cap interface were found to be critical factors in controlling Cu electromigration reliability. The adhesion of the Cu/cap interface can be directly correlated to electromigration MTF and activation energy. Results of present study suggest that interface of Cu interconnects is the key factor for EM performance for advanced BEOL technology design rules.

Stress Migration and Electromigration Improvement for Copper Dual Damascene Interconnection

Stress migration (SM) and electromigration (EM) were widely used to study the performance of interconnection process of metal/via formation in copper dual damascene of wafers. Necking and voids at the via bottom were important in causing failures in tests of stress migration and electromigration. In this report, the contamination of the bottom of via, which results in poor step coverage, the adhesion of seed layers, and poor copper grain formation are identified to be the underlying causes of the necking and void formation after the first EM and SM tests are performed. The contamination of the via formation processes included via etching, trench etching, and barrier/seed layer depositions. A well-shaped via profile can be optimized using three methods, the first involves Cu/SiN interface stress, the second involves Cu grain growth, and the third involves post via etching clean study. Eliminating the contamination of the via bottom and optimizing step coverage and adhesion of the barrier seed layers improve the EM and SM performance from to 59 s, in the copper-related processes for fabricating 300 mm wafers using technology that is beyond 0.13 μm technology. © 2004 The Electrochemical Society. All rights reserved.

Effects of Ti Addition on Via Reliability in Cu Dual Damascene Interconnects

We investigated the effects of a Ti addition on the reliability and the electrical performance of Cu interconnects, comparing three different ways of Ti addition such as A) Ti layer insertion under Ta-TaN stacked barrier metal, B) Ti layer insertion between a Ta-TaN barrier and Cu, and C) the Ti doping from the surface of the electrochemical-plated (ECP) Cu film. The structure-A drastically suppresses the stress-induced voiding (SIV) under the via connected to a wide lower line due to adhesion improvement by Ti at the via-bottom, while the electromigration (EM) is not improved. In the structure-B, by contrast, the EM is improved but the SIV resistance is degraded. The Ti doping from the bottom surface of Cu film restricts the grain growth and increases the tensile stress, enhancing the SIV. The structure-C improves not only the SIV but also the EM resistance. The oxygen gettering effect of Ti during the ECP-Cu annealing is a reason for the reliability improvements of the SIV and the EM. The improvement of adhesiveness at the interface between the via and the lower Cu line, and the oxygen gettering from Cu by Ti play an important role in suppressing the SIV and the EM.

Electromigration of Al-0.5 wt%Cu with Nb-Based Liner Dual Damascene Interconnects

The electromigration (EM) of Al-0.5 wt%Cu/Nb-based liner dual damascene (DD) interconnects is investigated for the first time. It is found that EM-induced voids nucleate in the line around the via at the cathode end of the line and their number decreases as the distance from the via becomes longer for the tungusten (W)-single damascene (SD)/aluminum (Al)-dual damascene (DD) interconnects. This fact indicates W-SD/Al-DD interconnects has mono-modal EM failure. Regarding the Al-SD/Al-DD interconnects, two types of layered liner, niobium (Nb)/long throw sputtered (LTS)-niobium nitride (NbN)/Nb and Nb/self ionized sputtered (SIS)-NbN/Nb, are applied and the EM failure mode is investigated. It is found that the Nb/LTS-NbN/Nb liner sample has bi-modal failure, which manifests as normal failure similar to W-SD/Al-DD interconnects and failure with long time to failure (TTF), probably due to the continuous atom flow at the sidewall or bottom of the via in the lower Al-SD interconnects. On the contrary, the Nb/SIS-NbN/Nb liner sample has mono-modal failure with a tight distribution of the EM log-normal distribution, resulting in a high EM reliability.

In situ observation of electromigration-induced void migration in dual-damascene Cu interconnect structures

In situ electromigration experiments were carried out to study electromigration-induced failure in the upper and lower layers in dual-damascene Cu test structures. The observations revealed electromigration-induced void movement along the Cu/dielectric cap interface. It supports the premise that Cu∕Si3N4 interface acts as the dominant electromigration path. However, the observed void nucleation occurs in the Cu∕Si3N4 interface at locations which are far from the cathode, and void movement along the Cu∕Si3N4 interface in opposite direction of electron flow eventually causes void agglomeration at the via in the cathode end. The different electromigration behaviors of the upper and lower layer dual-damascene structures are discussed.

Enhancing the efficiency of postetch polymer removal using megasonic wet clean for 0.13-μm dual damascene interconnect process

In this paper we discuss the use of high-frequency acoustic waves (approximately 0.8–1 MHz, megasonic) as a means of enhancing cleaning efficiency for postetch polymer removal in the Cu/low-k dual damascene process. Attempts were made to integrate 0.13-μm technology Cu/low-k dual damascene structures without hard mask, by using acoustic agitation as a means of improving process margin over fencing issues associated with this integration scheme. We have demonstrated that it is possible to use this method on 0.13-μm technology Cu/low-k dual damascene structures without damage. Contact resistance yields of more than 90% were still achievable, although the processing time was reduced significantly with the use of megasonic enhancement.

Impact of barrier metal on electrical performance of Cu/low K (Black Diamond™) in 0.13μm dual damascene interconnection

The impact of barrier metal on electrical performance of Cu/low K (Black Diamond™) in 0.13-μm dual damascene (DD) interconnection has been investigated. The via resistance and its distribution were reduced by using high-density plasma barrier metal (Ta) deposition technique. The average breakdown electrical field for samples with high-density plasma barrier metal (Ta) was increased to 2.4 MV/cm as compared to samples with conventional Ta deposition. Transmission electron microscope (TEM) images reveal that nonuniformity of barrier metal on the sidewall and bottom of the DD structure were significantly improved by applying high-density plasma barrier metal (Ta) deposition technique. Burn-in test at 200 °C for 1000 h was carried out, and it was found that there was no significant change of via resistance and line–line leakage behavior. The thickness of barrier metal was also optimized. Electrical results show that high-density plasma barrier metal deposition of 200 Å Ta improved electrical performance and enhanced the reliability of 0.13-μm dual damascene interconnection.

Characterization and performance of dielectric diffusion barriers for Cu metallization

For the required reduction in the effective dielectric constant of inter-metal dielectrics (IMD) and inter layer dielectrics (ILD) in Cu dual damascene interconnects (DDI), two potential low- k dielectric barrier materials, viz., SiCO and SiCN, were investigated and compared with conventional SiN film in terms of chemical composition and barrier resistance to Cu diffusion. Fourier transform infrared spectra (FTIR) indicate that the CH 3 group incorporated into SiCO and SiCN films may be responsible for a reduction in the dielectric constant. SiCO film exhibits a better Cu diffusion depth profile than SiCN film after annealing in the temperature range 200–400 °C. However, the Cu penetration SiCO may rapidly increase in the annealing temperature range of 500–600 °C. SiCN film exhibits a stable performance against Cu penetration over the temperature range of 200–800 °C.

Statistical Study for Electromigration Reliability in Dual-Damascene Cu Interconnects

This paper summarizes results from recent studies on electromigration (EM) reliability of Cu dual-damascene interconnects using a statistical approach. First, mass transport in Cu damascene structure was discussed, where the activation energies for oxide, porous MSQ (methylsilsesquioxane), and organic polymer dielectrics were found to be in the range of 0.8-1.0 eV, suggesting mass transport is dominated by interfacial diffusion at the Cu and SiN/sub x/ cap-layer interface regardless of the dielectric material. Then the impact of low-k inter-layer dielectrics on EM characteristics was investigated by measuring the critical product of current density and conductor length, (jL)/sub c/. Compared with oxide, the weaker mechanical strength of low-k dielectrics reduces (jL)/sub c/ due to less confinement and a smaller back flow stress gradient /spl Delta//spl sigma//L in Cu/low-k interconnects. Extrinsic failure due to interfacial delamination was observed in Cu/organic polymer interconnects, which caused further decrease in (jL)/sub c/. Complementing EM tests, Monte Carlo simulation was developed based on the weakest link approximation to separate the bimodal failure distribution into two individual lognormal distributions and deduce the characteristics of the weak-mode (early) and the strong-mode failures. Failure analysis using FIB confirmed the bimodal failure behavior with void formation at the cathode via bottom found to be responsible for the early failures.

Electromigration behavior of dual-damascene Cu interconnects––Structure, width, and length dependences

Experiments were performed to study the effect of line width and length, and the results revealed interesting differences in electromigration behavior of via-fed upper and lower layer dual-damascene test structures. The observed location of electromigration induced void in upper and lower layer test structures cannot be completely explained by the theory of current gradient induced vacancy diffusion. The electromigration median time to failure (MTF) were found to be dependent upon the line width for the lower layer test structures while it remained unaffected in the case of upper layer test structure. Cu/dielectric cap interface acting as the dominant electromigration path and the current crowding location being near the Cu/dielectric cap interface for lower layer structures due to structural differences, explain this behavior. Similarly, short length upper and lower layer test structures exhibited completely different characteristics. The back stress effect on short lines was evident on both upper and lower layer structures, however, only the upper layer showed two distinct via and line failure mechanisms. These observed effects are specific to Cu dual-damascene structures and can have major technological implications for electromigration reliability assessment.