DSP Processor Research Articles

Energy Aware 32 Bit Arithmetic and Logical Unit for Error Tolerant Applications

In this era of high end devices, the power efficient architecture is taking responsibility so as to reduce the cost for maintenance. This becomes the critical task for embedded based device, graphical based processor and similar DSP processors which suffers with low power. The core of every embedded device and processor which in turn uses ALU as the workhorse. As we know if workhorse require less power, speed and area so based on that workhorse complete system will make justice with SPAA metrics (Speed, Power, Area and Accuracy). This paper proposed an architecture of 32 bit General Purpose ALU .The critical power dissipation can be avoided by the application of clock gating of the hardware required and improving architectural approach for this in which we divide ALU is four sub block of 8-8 bit. These 32 bit ALU is identify input bit and according to that it will perform operation. Proposed architecture is combination of four 8 bit ALU which is accurate, semi accurate and approximate. Due to these logic we can save power consumption. The synthesized architecture is implemented by Hardware descriptive language (Verilog). Analysis is performing on FPGA (Field Programmable Gate Array) level.

Ambulance Siren Noise Reduction using LMS and FXLMS Algorithms

Objectives: In case of medical emergency, an ambulance uses siren (which produces noise up to 120 dB) to alert the traffic on the road to give way. However, siren noise is troublesome to the patient lying inside. This calls for noise control inside the ambulance. Methods/Statistical Analysis: The passive noise control methods are not feasible and economically inviable so active noise control (ANC) method is applied. The ANC is electro-acoustic technique in which the noise signal is acquired and noise with opposite phase is produced and overlapped on input noise to suppress the same. The weights are updated using adaptive algorithms so as to reduce the error in ANC system. In present work, Least Mean Square (LMS) and Filtered- Reference Least Mean Square (FxLMS) algorithm based ANC systems are applied and compared for ambulance siren noise reduction. MATLAB is used for simulating the ANC systems. Findings: Both the algorithms are compared on the basis of residual noise and Smoothened Ensemble Average Square Error (SEASE). From the results, it is found that both algorithms LMS and FxLMS are good in noise reduction. The noise reduction for FxLMS based ANC system is 28 dB whereas it is 25 dB for LMS based ANC system, which indicates the superiority of FxLMS algorithm over LMS algorithm. The results are obtained analytically as well as indicated by Power Spectral Density (PSD) plots of the residual noise. The comparison of SEASE for both algorithms also indicates better performance for FxLMS algorithm. The ANC system based on FxLMS algorithm is more stable as it considers the secondary path which includes practical components such as ADC, DAC, etc. Applications/Improvements: The results indicate that FxLMS algorithm based on ANC system can be implemented on the hardware using DSP processor. It can be further used for the other applications of noise reduction such as server noise, vacuum cleaner, etc.

Design and Implementation of Double Precision Floating Point Comparator

Floating point comparison is a fundamental arithmetic operation in DSP processor. The high dynamic range of floating point comparators find wide applications in sorting data problem, DSP algorithms etc. High performance with optimum area is a major concern for the practical implementation of these comparators. Another major concern with respect to the floating point numbers is the invalid numbers. Thus a separate module is required to handle the invalid numbers. In the present work, a double precision floating point comparator design is proposed for efficient floating point comparison. This comparator takes full advantage of the parallel prefix tree architecture. It first compares the most significant bit and proceeds towards least significant bit only when the compared bits are equal. Representation of floating point numbers is based on IEEE 754 standard. The double precision floating point comparator is modelled using Verilog HDL and synthesized in Xilinx ISE 14.6 targeting Virtex 5 and Cadence encounter tool. The results show that the new comparator architecture is efficient in handling all the invalid floating point numbers.

Hardware implementation of ECG denoising system using TMS320C6713 DSP processor

The electrocardiogram (ECG) signal is an extensively used biomedical signal for diagnosis of heart diseases. However, the quality of ECG signal is deteriorated by several noises during its acquisition. The two dominant and recurring noises are power line interference and baseline wander noise and they have to be removed for better clinical evaluation. This paper proposes a new ECG denoising system using a combination of Empirical Mode Decomposition (EMD) algorithm and FFT-based frequency analysis. The proposed ECG denoising system is first simulated and validated using MATLAB. Then, it is implemented in TMS320C6713 DSP processor using Code Composer Studio (CCS). The proposed system is tested with the standard ECG signals obtained from Massachusetts Institute of Technology-Beth Israel Hospital (MIT-BIH) Arrhythmia Database. The root mean square error (RMSE) and correlation coefficient are used as the evaluation measure to compare the performance of the proposed method with an existing denoising system. The experimental results with reduced RMSE value and the average correlation coefficient of 0.9889 between the original ECG and the denoised one indicate the successful removal of power line interference and baseline wander noise by the proposed ECG denoising system.

Real Time Suppression of Howling Noise in Public Address System

Howling noise is a common phenomenon in a public address system. It is built up due to the acoustic coupling between the speaker system and the microphone when it creates a positive feedback. Real time implementation of howling noise detection and suppression was implemented using TMS320C6713 DSK starter kit. The whole implementation was done based on direct memory access (DMA) feature of the DSP processor. The method uses the properties of howling noise for efficient detection and has the advantage of suppressing the noise. Howling detection is performed based on spectral flatness measure (SFM) of each input speech frame. For frames without howling, the input is passed as such to the output. Howling suppression is performed by making output samples as zero if the presence of howling noise is detected.

Robust Active Noise Control System for Fighter Aircraft Pilot Helmet Application

This paper proposes an Active Noise Control (ANC) scheme for fighter aircraft pilot helmet application. The proposed scheme addresses the noise environment inside the helmet to achieve perceivable noise attenuation. It also incorporates algorithms such as energy based detectors to control the operation of ANC system and variable step-size to increase the performance of ANC, to make the system robust. The paper highlights the real-time algorithm development on a DSP processor to meet the real-time resource constraints. The developed ANC system is evaluated in the laboratory for a typical fighter aircraft noise and the results when compared with the performance of existing system, found to be quite promising.

English

In this paper, we have designed an energy efficient Vedic Divider using an ancient Vedic mathematics technique known as Paravart- yaYojayet. ParavartyaYojayet is a Sanskrit name which means transpose and adjust. Vedic mathematical formulas are used to solve tedious and cum- bersome arithmetic operations. Today's world demands implementation of techniques which take lesser time and are energy efficient so we have de- signed a Vedic divider to solve long divisions in seconds. Our design con- sists of 2 inputs for dividend and divisor and 2 outputs that are remainder and quotient. Many researchers have done research work on Vedic mathe- matics to solve DSP operations using Urdhava-Triyagbhayam multiplica- tion sutra, to design asynchronous Vedic DSP processor core and lots more. In our paper we have implemented our code on Xilinx ISE Design Suite 14.2 and results were tested on 28nm FPGA platform. We have done power analysis by varying frequencies and capacitance to make our Vedic divider energy efficient. Analysis results that the maximum power is consumed at 2.2GHz and minimum power is consumed at 1.2GHz. In respect of capac- itance maximum power is consumed at 100pF and minimum power is con- sumed at 20pF.

Development of New Measuring Systems Based on Symmetric Components in Electric Networks

This paper describes real-time functions of development measuring system in distributive electric network and structure of the system for acquisition in systems for measuring, protection and control. Here are presented particularities of process and projecting of DSP processor in which base is digital filter that acquistions, processes and transfer to SCADA all data of possible failures in the moment of their occurrence and new models that are used in the system analysis (behaviour simulations) for the purpose of adjustment of parameters. It has been shown that the third harmonic is one of the most dominant quantities, which reliably and accurate describes situation in electric network.

Implementation Analysis of Binaural Audio Crosstalk Cancellation on Heterogeneous Parallel Computing platforms using Mixed Non-Uniform Partitioned Convolution

As general DSP processor architectures don’t have massive parallel architecture, they are not suitable to implement 3D audio virtual techniques at very long filters due to computational problems. To address these implementation issues of very long filters, an efficient method called Mixed Non-uniform Partitioned Convolution is proposed in this paper for implementing binaural audio crosstalk cancellation on heterogeneous parallel computing platforms. By using massive parallel architecture of heterogeneous platforms, the proposed approach is able to solve computational problems even at filter lengths of 65536 (32-bit floating point). The partitioning scheme followed in this paper is explained in detail to schedule partitions on various compute units of GPU device. The proposed approach was implemented on AMD GPUs using task parallel concept. The instruction level optimization was also provided for complex frequency multiplication and addition using OpenCL. The performance of this approach is compared against the existing techniques proposed by Garcia and Gardener. The cost vs. computational performance tradeoff comparison was given between proposed approach and existing methods. The comparison clearly shows that proposed approach is very efficient at very long filters and requires reasonable cost of implementation in terms of number of compute units. The combination of instruction level and algorithmic level optimizations make the proposed approach more suitable for implementation of not only stereo inputs based audio CTC but also multichannel inputs, particularly at very long filter lengths on parallel computing platforms.

Implementation of Adaptive Filters on TMS320C6713 using LabVIEW - A Case Study

Adaptive filters are playing a vital role in signal processing and communication filed of engineering for the purpose of filtering the unwanted signal, signal denoising, signal enhancement, etc. The main characteristic of the adaptive filter is the adjustment of filter coefficients dynamically with respect to the input signal which helps a lot in signal processing applications. This study main focus on implementing such adaptive filters on digital signal processors. The adaptive filtering algorithms such as Least Mean Square (LMS) algorithm and Normalized LMS (NLMS) algorithms are implemented with TMS320C6713 floating-point DSP processor using LabVIEW environment in real time. To test the functionality of the algorithms, the sinusoid signal is added with noisy and applied as an input the filter and the resultant denoising output is obtained with both the algorithms. We implement it with TMS320C6713 floating-point Digital Signal Processor using LabVIEW environment in real time. Our objective is to reduce or filter the noise using these algorithms and obtain the performance metrics like peak output, Mean Square Error (MSE), Peak Signal-to-Noise Ratio (PSNR) as a part of simulation results. The PSNR produced by the NLMS algorithm is obtained as 18.414 is very high as compared with 3.28416 produced by the LMS algorithm. Interfacing the TMS320C6713 DSP board with the LabVIEW application is done using the Code Composer Studio software tool. This study focuses the principle of adaptive filters by implementing the Least Mean Square (LMS) algorithm and Normalized LMS algorithms and can be further extended with Kalman filters too. er .

Real Time Implementation of Speaker Verification System

Verification of speakers is the use of the voice pattern to check the authenticity of the individual. In this paper the speaker verification system has been implemented on a real time DSP processor TMS3206713 with a new technique is proposed. Feature extraction and speaker modeling are the two major steps involved in speaker verification systems. Being the most frequently used features extracted from the human speech signal, the Mel Frequency Cepstral Coefficients (MFCC) have been considered for feature extraction. In the speaker modeling, a new technique known as Multi Section Vector Quantization (MSVQ) is implemented in addition to normal Vector Quantization. These techniques MFCC and VQ are generally used to recognize the speaker from a database of trained users. Using Multi Section Vector Quantization we can compare the trained codebook of particular user with the utterance and the authenticity decision can be made. Thus the advantage of using Multi Section Vector Quantization in speaker verification system is being discussed and the efficiency of this system is presented. To make this real time system robust in most of the environments a noise filter is also added during the pre-processing stage.

A sensory feedback system for prosthetic hand based on evoked tactile sensation.

The lack of reliable sensory feedback has been one of the barriers in prosthetic hand development. Restoring sensory function from prosthetic hand to amputee remains a great challenge to neural engineering. In this paper, we present the development of a sensory feedback system based on the phenomenon of evoked tactile sensation (ETS) at the stump skin of residual limb induced by transcutaneous electrical nerve stimulation (TENS). The system could map a dynamic pattern of stimuli to an electrode placed on the corresponding projected finger areas on the stump skin. A pressure transducer placed at the tip of prosthetic fingers was used to sense contact pressure, and a high performance DSP processor sampled pressure signals, and calculated the amplitude of feedback stimulation in real-time. Biphasic and charge-balanced current pulses with amplitude modulation generated by a multi-channel laboratory stimulator were delivered to activate sensory nerves beneath the skin. We tested this sensory feedback system in amputee subjects. Preliminary results showed that the subjects could perceive different levels of pressure at the tip of prosthetic finger through evoked tactile sensation (ETS) with distinct grades and modalities. We demonstrated the feasibility to restore the perceptual sensation from prosthetic fingers to amputee based on the phenomenon of evoked tactile sensation (ETS) with TENS.

High Speed Video System for Tissue Measurement Based on PWM Regulated Dimming and Virtual Instrumentation

Paper focuses on main topics in high speed video acquisition system designing. This video system is used in sophisticated diagnostics of microstructures in human tissue, especially respiratory epithelium cilium. System is linked with optical microscope and uses a phantom generator controlled with DSP processor for calibration and debugging. Algorithms and software are developed as user friendly virtual instruments.

High-Performance DSP Processors for Intelligence Applications

High-Performance DSP Processors for Intelligence Applications

Real time implementation of artificial neural networks‐based controller for battery storage supported wind electric generation

Energy storage systems have established their capability to overcome the problems caused by intermittent nature of renewable sources when integrated to existing grid. Voltage and frequency control, as well as load shifting can be done using grid level storage systems incorporated with renewable sources. They can effectively serve the system as an energy sink and source. Operational use of energy storage for grid level support of a wind electric generator (WEG) is demonstrated in this study. The battery storage supported WEG along with controllers is modelled. Artificial neural network controller, which is having inherent learning capability, is developed to regulate the power flow between wind generator and utility grid. The proposed algorithm and the corresponding controller are simulated in MATLAB/Simulink and implemented in the DSP processor. The real time data exchange between Simulink and the floating point DSP processor TMSF32028335 is realised using on-board JTAG emulator. The hardware implementation using DSP processor presented in this work establishes the efficacy of the proposed control strategy for real time applications.

Online Dynamic Compensation of Pressure Sensor

An online dynamic compensation of the pressure sensor based on simultaneous identification method of model order and parameter is proposed to identify the model of pressure sensor and set digital compensation links for the pressure sensor. While simulating, the compensation links can broaden the frequency band and improve the dynamic process of the pressure sensor. This article describes the realization of the digital dynamic compensation with DSP processor and the process of the experimental verification. The results show that the simultaneous identification method can be used in determination of model and digital compensation links for pressure sensor effectively. And DSP measurement device can complete online dynamic compensation effectively.

BIT EFFICIENT RESIDUE NUMBER SYSTEM BASED LOW POWER RECONFIGURABLE DSP PROCESSOR

In modern era of advanced computing and high end multimedia there is a need for low power reliable and portable electronic systems. Even though many techniques have been proposed to reduce power over the years, out of all, the best possible solution, so far has been to over scale the power supply. When a system is over scaled the power reduces drastically but this also increases the complexity of the design. The other alternate is to replace the conventional binary number systems with Residue Number System. The residue number system is a non-weighted number system which speeds up arithmetic operations by dividing them into smaller parallel operations and provides carry-free addition, multiplication and borrow-free substraction operations. In this paper we propose a technique to reduce power based on bit efficient Residue Number System with a proper choice of prime moduli . Here we consider a Digital Signal Processor that can be reconfigured as a case study. The technique proposed can reduce power upto 34 percent thn a conventional binary number system based DSP Processor

Speed control of Brushless DC motor using bat algorithm optimized Adaptive Neuro-Fuzzy Inference System

In this paper, speed control of Brushless DC motor using Bat algorithm optimized online Adaptive Neuro-Fuzzy Inference System is presented. Learning parameters of the online ANFIS controller, i.e., Learning Rate (η), Forgetting Factor (λ) and Steepest Descent Momentum Constant (α) are optimized for different operating conditions of Brushless DC motor using Genetic Algorithm, Particle Swarm Optimization, and Bat algorithm. In addition, tuning of the gains of the Proportional Integral Derivative (PID), Fuzzy PID, and Adaptive Fuzzy Logic Controller is optimized using Genetic Algorithm, Particle Swarm Optimization and Bat Algorithm. Time domain specification of the speed response such as rise time, peak overshoot, undershoot, recovery time, settling time and steady state error is obtained and compared for the considered controllers. Also, performance indices such as Root Mean Squared Error, Integral of Absolute Error, Integral of Time Multiplied Absolute Error and Integral of Squared Error are evaluated and compared for the above controllers. In order to validate the effectiveness of the proposed controller, simulation is performed under constant load condition, varying load condition and varying set speed conditions of the Brushless DC motor. The real time experimental verification of the proposed controller is verified using an advanced DSP processor. The simulation and experimental results confirm that bat algorithm optimized online ANFIS controller outperforms the other controllers under all considered operating conditions.

A Pipelined Fused Processing Unit for DSP Applications

This paper designs a processing element for FFT processor capable of operating on 32-bit double precision floating point numbers. Pipelining is performed on the computational elements of the DSP processor to enhance the throughput. The performance of the Processing unit is increased by using the concept of fused architecture on the sub modules – the dot product unit and the add sub unit. Pipelining increases the speed of the CE of the processor while fused operations claim area optimization. The DSP applications involve FFT Processors that make use of the butterfly operations consisting of multiplications, additions, and subtractions of complex valued data (data is split into real part and the imaginary part). The radix-2 and radix-4 butterflies are designed using fused architecture. The fused FFT butterflies are to be 20 percent speedier and 30 percent smaller in area compared with the conventional method. The processing unit covers almost all the computations necessary for the processor.

Design and Implementation Analysis of OSD based Audio Crosstalk Cancellation with Multi-Channel Inputs on DSP Processors

To overcome the basic system inversion problems in conventional crosstalk cancellation systems, the three channel Optimum Source Distribution (OSD) was developed by Takashi et al., that provides balance between in-phase and out of phase components. The main difficulty in this system is real-time implementation of cross talk cancellation filters on DSP platforms, particularly when filter lengths are very long with system operates on multichannel inputs. This paper discusses the implementation complexities and proposes an efficient approach to reduce the power consumption. It also discusses efficient usage of available processor memory. By utilizing the processor resources and existing frequency domain techniques, this approach would be one of best methods for long filters. The mathematical model, with efficient design for floating point DSP processors, clearly explains the optimization methods at algorithmic and instruction levels. The computational complexity of the proposed method was measured for various multi-channel input sources and the comparison was shown. The results indicate that the proposed method provides efficient computations than existing methods. Keywords: Convolution, Crosstalk Cancellation, Optimal Source Distribution, Overlap Save Method, Uniform Partitioned Convolution