BIT EFFICIENT RESIDUE NUMBER SYSTEM BASED LOW POWER RECONFIGURABLE DSP PROCESSOR

Abstract

In modern era of advanced computing and high end multimedia there is a need for low power reliable and portable electronic systems. Even though many techniques have been proposed to reduce power over the years, out of all, the best possible solution, so far has been to over scale the power supply. When a system is over scaled the power reduces drastically but this also increases the complexity of the design. The other alternate is to replace the conventional binary number systems with Residue Number System. The residue number system is a non-weighted number system which speeds up arithmetic operations by dividing them into smaller parallel operations and provides carry-free addition, multiplication and borrow-free substraction operations. In this paper we propose a technique to reduce power based on bit efficient Residue Number System with a proper choice of prime moduli . Here we consider a Digital Signal Processor that can be reconfigured as a case study. The technique proposed can reduce power upto 34 percent thn a conventional binary number system based DSP Processor