DSP Processor Research Articles

The Design of Embedded Video Monitoring System Based on DSP Processor

This paper designs a embedded video monitoring system based on ARM processor Ep9315 and TMS320DM642, and using embedded Linux operating system. In the system, video capturing module uses the video decoder TW2814. In order to capture better data, the control of TW2814 is needed. Through the imitation of I2C bus, the driver provide the application with the function of the setting of capturing parameters such as hue, color saturation, contrast and brightness, and the check of video losing.

Non-Uniformity Correction Algorithm Research Based on One FPGA Processor

The two-point non-uniformity correction based on Least mean square (LMS) algorithm which was proposed by Suxia Xing need one FPGA processor, one DSP processor and four SRAM chips. This will increase the cost and volume of the whole infrared system. In the LMS algorithm, this paper improves the estimation of the ideal signal, so that it can reduce the influence of blind elements and improve the effect of non-uniformity correction. Besides, this paper realizes the two-point non-uniformity correction based on LMS algorithm with only one FPGA processor and two SRAM chips in the final, this will reduce the volume, weight, cost of the whole infrared system. Comparing with the two-point non-uniformity correction based on one FPGA processor, this paper did not need blackbody with uniform radiation in system. Above all, the method of this paper is useful and practical.

A Novel Hybrid Negative Half Cycle Biased Modulation Scheme for Cascaded Multilevel Inverter

This paper proposes a new Modified hybrid modulation scheme for cascaded multilevel inverter. The proposed method employs novel single carrier sinusoidal pulse width modulation with its negative cycle biased (HNHCBM) for reducing switching losses when compared to other sinusoidal modulation methods using a hybrid scheme. This scheme is a derivative of various single carrier sinusoidal pulse width modulation scheme and main advantages are reduced harmonics, enhanced output voltage, reduced power loss in the series cells and ease of implementation. The simulation results are analysed with matlab/simulink and compared with experimental results obtained using DSP processor TMS320F2407 by applying it to 5-level inverter and the results are summarized. DOI: http://dx.doi.org/10.11591/ijpeds.v4i2.5696

Examination of Electromagnetic Noises and Practical Operations of a PMSM Motor driven by a DSP and Controlled by means of Field Oriented Control

This paper presents main problems of practical implementation of filed oriented control (FOC) dedicated for a permanent magnet synchronous motor (PMSM). By means of this work, elements of FOC’s mathematical model and practical implementation of the electronic commutator are presented. It is based on the DSP processing unit IGBT power module. The measurement system consists of control unit equipped with inverter and encoder. The main element of driving system is PMSM drive. There are two main problems addressed in this paper: electromagnetic distortions and proper calculations in real systems. This work is intended to resolve these problems. Described solutions have been implemented and examined practically. DOI: http://dx.doi.org/10.5755/j01.eee.20.5.7099

A HIGH SPEED VLSI ARCHITECTURE FOR DIGITAL SPEECH WATERMARKING WITH COMPRESSION

The need to provide a copy right protection on digital watermarking to multimedia data like speech, image or video is rapidly increasing with an intensification in the application in these areas. Digital watermarking has received a lot of attention in the past few years. A hardware system based solely on DSP processors are fast but may require more area, cost or power if the target application requires a large amount of parallel processing. An FPGA co-processor can provide as many as 550 parallel multiply and accumulate operations on a single device, but FPGAs excel at processing large amounts of data in parallel, as they are not optimized as processors for tasks such as periodic coefficient updates, decision- making control tasks. Combination of both the FPGA and DSP processor delivers an attractive solution for a wide range of applications. A hardware implementation of digital speech watermarking combined with speech compression, encryption on heterogeneous platform is made in this paper. It is observed that the proposed architecture is able to attain high speed while utilizing optimal resources in terms of area.

Register swapping schemes for low power execution

For embedded systems, the power dissipation on buses has become an essential issue in recent years. Many real-time embedded processors, such as DSP processors, adopt the Harvard architecture in which the data and instruction buses are separated to avoid processing-speed degradation. The power dissipation on an instruction bus can be reduced if the switching activities between consecutive instructions on that bus are reduced. Two efficient algorithms, the greedy method and the dynamic programming based method, are proposed to swap commutative source register fields of adjacent instructions. The switching activities on the instruction bus are therefore reduced, without affecting the execution results. Experimental results show that the proposed schemes result in a reduction of as much as 21.43% in the switching activities of consecutive source register fields between commutative blocks. In addition, the proposed schemes can be conveniently integrated with other encoding schemes to further improve the power dissipation on an instruction bus.

Design of Small MEMS Microphone Array Systems for Direction Finding of Outdoors Moving Vehicles

In this paper, a MEMS microphone array system scheme is proposed which implements real-time direction of arrival (DOA) estimation for moving vehicles. Wind noise is the primary source of unwanted noise on microphones outdoors. A multiple signal classification (MUSIC) algorithm is used in this paper for direction finding associated with spatial coherence to discriminate between the wind noise and the acoustic signals of a vehicle. The method is implemented in a SHARC DSP processor and the real-time estimated DOA is uploaded through Bluetooth or a UART module. Experimental results in different places show the validity of the system and the deviation is no bigger than 6° in the presence of wind noise.

EFFICIENT FPGA BASED MATRIX MULTIPLICATION USING MUX AND VEDIC MULTIPLIER

Most of the algorithms which are used in DSP, image and video processing, computer graphics, vision and high performance supercomputing applications require multiplication and matrix operation as the kernel operation.In this paper, we propose Efficient FPGA based matrix multiplication using MUX and Vedic multiplier. The 2x2, 3x2 and 3x3 MUX based multipliers are designed. The basic lower order MUX based multipliers are used to design higher order MxN multipliers with a concept of UrdhvaTiryakbyham Vedic approach. The proposed multiplier is used for image processing applications. It is observed that the device utilization and combinational delay are less in the proposed architecture compared to existing architectures.

HIGH SPEED MULTIPLIER USING VEDIC MATHEMATICS

The digital signal processing in today’s time need high speed computation. The basic building block of signal processing in Communication, Biomedical signal processing, and Im age processing remains Fast Fourier Transform (FFT) . FFT computation involves multiplications and additions. Speed of th e DSP processor mainly depends on the speed of the multiplier. Time delay, power dissipation and the silicon chip area. These are th e most important parameters for the fast growing te chnology. The conventional multiplication method requires more time and area a nd hence more power dissipation. In this paper an a ncient Vedic multiplication method called “Urdhva Triyakbhyam” is implemented. It is a method based on 16 sutras of Vedic mathemat ics. Vedic Mathematics reduces the number of operations to be carried out compared to the conventional method. The code descr iption is simulated and synthesized using FPGA device Spartan XC3S400-PQ208 .

FPGA Implementation of Latency, Computational time Improvements in Matrix Multiplication

Matrix operations, like matrix multiplication, are commonly used in almost all areas of scientific research. Matrix multiplication has significant application in the areas of graph theory, numerical algorithms, signal processing, and digital control. Matrix multiplication is a computationally intensive problem, especially the design and efficient implementation on an FPGA where resources are very limited, has been more demanding. FPGA based designs are usually evaluated using three performance metrics: speed (latency), area, and power (energy). Fixed point implementations in FPGA are fast and have minimal power consumption. With today’s applications requiring ever higher computational throughputs, distributed memory approach is an effective solution for real-time applications. This application shows how to achieve higher computational throughput via parallel processing with the DSP processors. The matrix-vector multiplication applied to calculate linear convolution. This paper presents an FPGAbased hardware realization of matrix multiplication based on distributed memory approach architecture. We propose an architecture that is capable of handling matrices of variable sizes our designs minimize the gate count, area, improvements in latency, computational time, and throughput for performing matrix multiplication and reduces the number of multiplication and additions hardware required to get the matrices multiplied on commercially available FPGA devices.

Performance Analysis of Low Power Bypassing-Based Multiplier

In the recent year growth of the portable electronics is forcing the designers to optimize the existing design for better performance. Multiplication is the most commonly used arithmetic operation in various applications like, DSP processor, math processor and in various scientific applications. In this paper a low power bypassing -based multiplier design is present, in which reduction in power is to be achieved in changed partial products of column bypassing multiplier as compared to column bypassing multiplier by exchange NOR gates with AND gates in the conventional multiplier I.e. in the design of conventional multiplier rather than AND gate, NOR gate is employed victimization DeMorgan’s theorem. Compare with 32×32 bits typical (parallel array) multiplier and column bypassing multiplier, this planned system consume less power.

Visual Motion Sensors and Neuromorphic Obstacle Avoidance System

In this work, we present motion detection algorithms that are based not only on biological models but also on the computational properties of motion perception. First, we describe monolithic implementations of hysteretic winner-take-all and nonlinear differentiator based algorithms. Second, we explain multi-chip implementations of biomimetic intensity-based models, namely Adelson-Bergen model. In addition, we describe an obstacle avoidance algorithm that is realized by incorporating a multi-chip version of the Adelson-Bergen algorithm with centering behavior and time-to-collision computation. In this way, the overall system can successfully acquire clues about the structure of its environment so that collisions can be effectively avoided. This system might be employed in building a robot that can navigate in complex cluttered environments. I. Introduction In this we describe an obstacle avoidance algorithm based on the system level implementation of the Adelson-Bergen multi-chip sensor integrated with centering and escape behaviors. As with biological systems, perception of motion information occupies a vital role in behavioral tasks achieved by artificial systems. It is utilized for tracking, collision avoidance, object recognition, time-to-flight computation, guidance, balance, and postural control.CCC In building biologically inspired architectures, it always has to be taken into consideration that biological models are by their nature continuous-time systems and they operate by employing a massively parallel processing strategy. These biological principles can be efficiently utilized in visual computations. In contrast to other sensory computations, optic flow computation is a very intensive process that is constrained by power consumption, and employing such technology definitely improves the performance of built systems. In addition, conventional design approaches in image processing that are implemented by employing a CCD camera together with a DSP processor cause problems such as an image transfer bottleneck, temporal aliasing and high power consumption. These systems work at high frequencies to deliver image information in a timely way and in achieving this they have to consume considerable amounts of power. Whereas, an integrative approach by analog VLSI technology and neuromorphic design principles makes intensive visual computations possible to be realized in power and space efficient systems. In contrast to conventional designs, these systems are data driven, that is, the output is sampled when there is a demand. Hence they consume little power and yield temporal aliasing-free computation. Inspired by biological models in the visual pathways of organisms and by computational properties of visual motion perception, a variety of visual motion sensors, which consume little power and work in real time, have been developed to solve problems faced in optical flow computation.

Intelligent Fault Identification System for Transmission Lines Using Artificial Neural Network

Transmission and distribution lines are vital links between generating units and consumers. They are exposed to atmosphere, hence chances of occurrence of fault in transmission line is very high, which has to be immediately taken care of in order to minimize damage caused by it. This paper focuses on detecting the faults on electric power transmission lines using artificial neural networks. A feed forward neural network is employed, which is trained with back propagation algorithm. Analysis on neural networks with varying number of hidden layers and neurons per hidden layer has been provided to validate the choice of the neural networks in each step. The developed neural network is capable of detecting single line to ground and double line to ground for all the three phases. Simulation is done using MATLAB Simulink to demonstrate that artificial neural network based method are efficient in detecting faults on transmission lines and achieve satisfactory performances. A 300km, 25kv transmission line is used to validate the proposed fault detection system. Hardware implementation of neural network is done on TMS320C6713. Keywords: Transmission Line, Asymmetric fault detection, Artificial neural network (ANN), Back Propagation algorithm, DSP processor TMS320C6713, Code Composer Studio, MATLAB/Simulink

Real-time loss minimization control in induction machines based on DSP TMS320LF2812

This paper presents a DSP based implementation of simple and very useful control algorithm for the real-time efficiency optimization of the indirect vectorcontrolled induction motor drives. Conventional field-oriented induction motor drives operate at rated flux even at low load. To improve the efficiency of the existing induction motors, it is important to regulate the magnetization flux of the motor in the desired operating range. This paper presents techniques for minimizing power loss (the copper and core losses) of induction motor based on determination of an optimum flux level for the efficiency optimization of the vector-controlled induction motor drive. An induction motor (IM) model in d-q coordinates is referenced to the rotor magnetizing current. Thus the decomposition into d-q components in the steady-state motor model can be utilized in deriving the motor loss model. The algorithm offers a fast convergence. The complete closed loop vector control of the proposed LMC-based IM drive is successfully implemented in real-time using digital signal processor DSP TMS320LF2812 for 1HP motor induction motor. The close agreement between the simulation by Matlab/Simulink and the experimental results confirms the validity and usefulness of the proposed techniques. The proposed LMC in a comparison with conventional FOC can reduce total losses from 5% to 67.2% for all load ranges.

도로 소음 저감을 위한 능동소음제어 시스템의 개발 및 기초실험

PURPOSES : The purpose of this study is about noise which is generated from roads and is consist of irregular frequency variation from low frequency to various band. The existing methods of noise reduction are sound barrier that uses insulation material and absorbing material or have applied passive technology of noise reduction by devices. The total frequency band is needed to apply active noise control. METHODS : In this study applies to the field of road traffic environment, signal processing controller and various analog signal input/output, the amplifier module is based on parallel-core embedded processor designed. DSP performs the control algorithm of the road traffic noise. Noise sources in the open space performance of evaluation were applied. In this study, controller of active signal processor was designed based on the module of audio input/output and main controller of embedded process. The controller of active signal processor operates noise reduction algorithm and performance tests of noise reduction in inside and outside environment were executed. RESULTS : The signal processing controller with OMAP-L137 parallel-core processors as the center, DSP processors in the active control operations dealt with quickly. To maximize the operation speed of an object and ARM processor is external function keys and display for functions and evaluating the performance management system was designed for the purpose of the interface. Therefore the reduction of road traffic noise has established an electronic controller-based noise reduction. CONCLUSIONS : It is shown that noise reduction is effective in the case of pour tonal sound and complex tonal sound below 500Hz by appling to Fx-LMS.

Research on Resistivity Measurement System of Submarine Sediment

This paper developed a resistivity measurement system on the platform of in-situ detector which based on seafloor drilling machine. In order to precisely process the weak voltage signal which outputted by the resistivity probe, the paper carried out the cross-correlation algorithm theoretical derivation and MATLAB simulation, then ported the algorithm to TMS320F28069 DSP processor and designed hardware. A mass of contrast experiment shows that the cross-correlation algorithm is an effective method to process weak signal. It can improve accuracy and anti-jamming ability of the submarine sediment resistivity measurement system. The method of submarine sediment resistivity measurement can be widely used in fields of marine geological survey, marine environment research, etc.

Application of Cross-Correlation Algorithm in Submarine Sediment Resistivity Measurement

This paper developed a resistivity measurement system on the platform of in-situ detector which based on seafloor drilling machine. In order to precisely process the weak voltage signal which outputted by the resistivity probe, the paper carried out the cross-correlation algorithm theoretical derivation and MATLAB simulation, then ported the algorithm to TMS320F28069 DSP processor and designed hardware. A mass of contrast experiment shows that the cross-correlation algorithm is an effective method to process weak signal. It can improve accuracy and anti-jamming ability of the submarine sediment resistivity measurement system. The method of submarine sediment resistivity measurement can be widely used in fields of marine geological survey, marine environment research, etc.

Robust Automatic Speech recognition System Implemented in a Hybrid Design DSP-FPGA

The aim of this work is to reduce the burden task on the DSP processor by transferring a parallel computation part on a configurable circuits FPGA, in automatic speech recognition module design, signal pre-processing, feature selection and optimization, models construction and finally classification phase are necessary. LMS filter algorithm that contains more parallelism and more MACs (multiply and Accumulate) operations is implemented on FPGA Virtex 5 by Xilings , MFCCs features extraction and DTW( dynamic time wrapping ) method is used as a classifier. Major contribution of this work are hybrid solution DSP and FPGA in real time speech recognition system design, the optimization of number of MAC-core within the FPGA this result is obtained by sharing MAC resources between two operation phases: computation of output filter and updating LMS filter coefficients. The paper also provides a hardware solution of the filter with detailed description of asynchronous interface of FPGA circuit and TMS320C6713-EMIF component. The results of simulation shows an improvement in time computation and by optimizing the implementation on the FPGA a gain in space consumption is obtained.

Carrier-Phase Differential GPS/INS Integrated Navigation System

According to high accuracy demand in the measurement field, this paper designs a high precision inertial measurement system by using DSP and ARM processor to realize carrier-phase differential GPS/INS integrated navigation. This paper chooses Kalman filter to estimate the systematic error, uses closed loop method to correct, and carries out carrier-phase differential GPS/INS data fusion. Through manipulating actual measurement data, the integrated navigation results indicate that position accuracy reaches cm level; velocity accuracy reaches cm/s level and attitude achieves high precision. The experiment proves the feasibility and effectiveness of carrier-phase differential GPS/INS integrated navigation system.

Electromechanical Actuator Control System Development Using Rapid Prototyping Method

In order to rapidly develop the control system of the Electromechanical Actuator (EMA), the DSP development platform is established using rapid prototyping method based on the MATLAB software, and all the models is configured and researched. First, the DSP development platform structure in the environment of MATLAB is mainly presented. And the operation principle has been showed. Then, the EMA control circuit board schematic diagram is necessarily introduced, which one is for the developer to conveniently configure the system model. Finally, the developer reasonably configures the control system models used in the Simulink library and constitutes them to speed closed loop control system of the EMA. The EMA control system code will be compiled and debugged rapidly through this platform. The executed program will automatically download into the DSP processor. And the result of debugging would be sent to the CAN bus receiver. For generally speaking, the difficulty of EMA control system code development method is reduced and the development cycle is shortened using this rapid prototyping method. And this system development method is fast and effective.