Abstract
The digital signal processing in today’s time need high speed computation. The basic building block of signal processing in Communication, Biomedical signal processing, and Im age processing remains Fast Fourier Transform (FFT) . FFT computation involves multiplications and additions. Speed of th e DSP processor mainly depends on the speed of the multiplier. Time delay, power dissipation and the silicon chip area. These are th e most important parameters for the fast growing te chnology. The conventional multiplication method requires more time and area a nd hence more power dissipation. In this paper an a ncient Vedic multiplication method called “Urdhva Triyakbhyam” is implemented. It is a method based on 16 sutras of Vedic mathemat ics. Vedic Mathematics reduces the number of operations to be carried out compared to the conventional method. The code descr iption is simulated and synthesized using FPGA device Spartan XC3S400-PQ208 .
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