Design and Implementation of Double Precision Floating Point Comparator

Abstract

Floating point comparison is a fundamental arithmetic operation in DSP processor. The high dynamic range of floating point comparators find wide applications in sorting data problem, DSP algorithms etc. High performance with optimum area is a major concern for the practical implementation of these comparators. Another major concern with respect to the floating point numbers is the invalid numbers. Thus a separate module is required to handle the invalid numbers. In the present work, a double precision floating point comparator design is proposed for efficient floating point comparison. This comparator takes full advantage of the parallel prefix tree architecture. It first compares the most significant bit and proceeds towards least significant bit only when the compared bits are equal. Representation of floating point numbers is based on IEEE 754 standard. The double precision floating point comparator is modelled using Verilog HDL and synthesized in Xilinx ISE 14.6 targeting Virtex 5 and Cadence encounter tool. The results show that the new comparator architecture is efficient in handling all the invalid floating point numbers.