ΔΣ Analog-to-digital Converter Research Articles

Analysis and Design of Noise-Shaping SAR ADC with Capacitor Stacking and Buffering

The noise-shaping (NS) successive-approximation-register (SAR) is a promising analog-to-digital converter (ADC) architecture which combines the benefits of SAR and Delta-Sigma (ΔΣ) ADCs. Among the various NS-SAR approaches, the recent emerged one with capacitor stacking and buffering exhibits excellent energy efficiency. This paper presents a tutorial for the design of NS-SAR ADC with capacitor stacking and buffering. The fundamental principle of the NS-SAR loop filter is analyzed, an ADC design example is provided, and the circuit implementation details with considerations on the non-idealities and trade-offs are discussed. This paper can be used as a tutorial for designing high-resolution and high-order NS-SAR ADC.

An 88 dB SNDR 100 kHz BW Sturdy MASH Delta-Sigma Modulator Using Self-Cascoded Floating Inverter Amplifiers

Battery-powered Internet-of-Things applications require high-resolution, energy-efficient analog-to-digital converters (ADCs). There are still limited works on sub-MHz-bandwidth ADC designs. This paper presents a sturdy multi-stage shaping (SMASH) discrete-time (DT) delta-sigma modulator (DSM) structure using a self-cascoded floating-inverter-based dynamic amplifier (FIA). The proposed structure removes the explicit quantization error extraction of the first loop and all the feedback DACs in the cascaded loop, decreasing the design complexity of the circuit. This enables the proposed DT DSM to operate at a higher speed, which is suitable for achieving high-order noise at a low oversampling ratio (OSR). The proposed self-cascoded FIA is more power-efficient and can acquire more than 45 dB DC gain under a 1.2 V supply. The DT DSM implemented in a piece of 55 nm CMOS technology measures an 88.0 dB peak signal-to-noise-and-distortion ratio (SNDR) in a 100 kHz bandwidth (BW) and an 85.3 dB dynamic range (DR), consuming 249.1 μW from a 1.2 V supply at 10 MS/s. The obtained 174.0 dB SNDR-based Schreier figure-of-merit (FoMs) is competitive within state-of-art high-resolution (SNDR > 85 dB) and general-purpose (sub-MHz-bandwidth) ΔΣ ADCs.

A High-Resolution Discrete-Time Second-Order ΣΔ ADC with Improved Tolerance to KT/C Noise Using Low Oversampling Ratio.

This work presents a novel ΣΔ analog-to-digital converter (ADC) architecture for a high-resolution sensor interface. The concept is to reduce the effect of kT/C noise generated by the loop filter by placing the gain stage in front of the loop filter. The proposed architecture effectively reduces the kT/C noise power from the loop filter by as much as the squared gain of the added gain stage. The gain stage greatly relaxes the loop filter's sampling capacitor requirements. The target resolution is 20 bit. The sampling frequency is 512 kHz, and the oversampling ratio (OSR) is only 256 for a target resolution. Therefore, the proposed ΔΣ ADC structure allows for high-resolution ADC design in an environment with a limited OSR. The proposed ADC designed in 65 nm CMOS technology operates at supply voltages of 1.2 V and achieves a peak signal-to-noise ratio (SNR) and Schreier Figure of Merit (FoMs) of 117.7 dB and 180.4 dB, respectively.

A 2-2 MASH ΔΣ ADC with fast-charge CLS input buffer and dual double sampling achieving 103.3-dB SNDR and ±2.5-ppm/FSR INL

This paper presents a 2-2 multi-stage-noise-shaping (MASH) ΔΣ analog-to-digital converter (ADC), in which an integrator with dual double sampling (DDS) technique and stability compensation is proposed to save the area of capacitors without increasing the thermal noise. In addition, a fast-charge correlated-level-shifting (CLS) input buffer is also proposed to improve the linearity with acceptable power consumption. The buffer and the ADC are fabricated in a 0.18-μm CMOS process with an active area of 2.41 mm2, with 3∼5V supply voltage for the input buffer and 1.8-V power supply for the ADC, the overall ADC chip achieves a signal-to-noise-and-distortion ratio (SNDR) of 103.3 dB, a spurious-free dynamic range (SFDR) of 113.2 dB and an integral nonlinearity (INL) of ±2.5 ppm/full-scale range (FSR). The overall power consumption is 14.88 mW.

An Energy-Efficient and Artifact-Resilient ASIC for Simultaneous Neural Recording and Optogenetic Stimulation.

This paper presents an application-specific integrated circuit (ASIC) fabricated using the CMOS 180 nm process to perform simultaneous neural recording and optogenetic stimulation. To perform effective optogenetic stimulation, the ASIC features an advanced switched-capacitor-based stimulation (SCS) driver, called voltage-boosting SCS (VB-SCS). The VB-SCS can drive LED with large current pulses up to 8 mA while reducing the required supply voltage by half, facilitating wireless power reception. To prevent saturation from stimulation-induced artifacts, the ASIC integrates a direct digitizing recording frontend with a high-resolution delta-sigma (ΔΣ) analog-to-digital converter (ADC) that directly digitizes neural signals with a large input dynamic range. This ΔΣ ADC involves a Gm-C integrator followed by a noise-shaping (NS) successive approximation register (SAR) quantizer. Measurement results indicate that this ΔΣ ADC-based direct digitizing frontend can tolerate large artifacts up to 300 mVPP while linearly digitizing neural signals with an effective number of bits (ENOB) of 11.4 bits, consuming 10.8 μW. The ASIC, together with its associated passive components, was assembled into a headstage for in vivo verification, successfully demonstrating the functionality of the ASIC.

A 4th-Order 4-Bit Continuous-Time ΔΣ ADC Based on Active–Passive Integrators With a Resistance Feedback DAC

This article reports a fourth-order continuous-time (CT) delta–sigma modulator (DSM) that features a single-amplifier biquad, a passive integrator, and an active integrator. This simplifies the circuit to only two op-amps in comparison to four power-hungry op-amps used in a conventional fourth-order DSM. In addition to improving the power consumption, the proposed design also has more relaxed requirements for the gain–bandwidth product and the loop gain. A 4-bit flash analog-to-digital converter (ADC) and two feedback digital-to-analog converters (DACs) are employed in this design to implement a fully integrated CT DSM. By incorporating the passive network in front of the last active integrator, this design gives a better attenuation at high frequency, which decreases the possibility of instability caused by out-of-band high-frequency signals. The proposed design has a measured bandwidth of 2 MHz with a power consumption of only around 3 mW. The effective number of bits (ENOB) of the proposed CT-DSM is approximately 12.7 bits with a peak signal-to-noise and distortion ratio (SNDR) around 78 dB, and it also exhibits a good Schreier figure of merit on the order of 166 dB compared to the existing state of the art.

Linearity Enhancement of VCO-Based Continuous-Time Delta-Sigma ADCs Using Digital Feedback Residue Quantization

A linearity enhancement scheme for voltage-controlled oscillator (VCO)-based continuous-time (CT) delta-sigma (ΔΣ) analog-to-digital converters (ADCs) is proposed. Unlike conventional input feedforwarding techniques, the proposed feedforwarding scheme using digital feedback residue quantization (DFRQ) can avoid the analog summing amplifier, allow intrinsic anti-aliasing filtering (AAF) characteristic, and cause no switching noise injection into the input. A VCO-based CT ΔΣ ADC adapting the proposed DFRQ enables residue-only processing in the quantizer, avoiding the degradation of signal-to-noise and distortion ratio (SNDR) due to VCO nonlinearity. The use of DFRQ also reduces the voltage swing of integrators without the drawbacks caused by conventional input feedforwarding techniques. The performance evaluation results indicate that the proposed VCO-based CT ΔΣ ADC with DFRQ provides 30.3-dB SNDR improvement, reaching up to 83.5-dB in 2-MHz signal bandwidth.

Analysis and Comparison of Readout Architectures and Analog-to-Digital Converters for 3D-Stacked CMOS Image Sensors

This review paper presents an overview of readout architectures and analog-to-digital converters (ADCs) for 3D-stacked CMOS image sensors (CIS) with their advantages and challenges. Depending on the application requirements, a suitable 3D-stacked readout architecture will be proposed. While most ADCs to date have been reported in planar CIS, this paper ports these designs to a 3D-stacked CIS and compares the different ADC topologies for this 3D-stacked context in terms of noise, speed and power efficiency. The comparison shows that the ramp and incremental ΔΣ ( IΔΣ) ADCs can achieve a better overall performance compared to the SAR and cyclic ADCs by a factor of ~3 better for 3D-stacked CIS. In addition, ramp and IΔΣ ADCs can both achieve (very) low fixed-pattern noise values.

A true random number generator that utilizes thermal noise in a programmable system‐on‐chip (PSoC)

SummaryThis study presents four designs for a true random number generator (TRNG) for Cypress programmable system‐on‐chip (SoC) (PSoC) devices, whose entropy source is the thermal noise of resistors. The first design includes a ΔΣ analog‐to‐digital converter (ADC) with two external resistors of 6 MΩ, where the resolution was set to 16 bits. The second, third, and fourth designs adopt the internal resistors of a programmable gain amplifier (PGA) as a noise source. The second design adopts a single‐stage PGA (gain 50) with a ΔΣ ADC, while the third design adopts a two‐stage PGA (gain 50 × 50) with a ΔΣ ADC. The fourth design adopts a trans‐impedance amplifier (TIA) with a ΔΣ ADC. All four designs have passed the National Institute of Standards and Technology (NIST) test suite.

Synthesizable lead-lag quantization technique for digital VCO-based ΔΣ ADC

This paper presents a synthesizable lead-lag quantization technique for all-digital delta sigma (ΔΣ) analog-to-digital converters (ADCs) based on voltage-controlled oscillator (VCO). Synthesizable circuitry is proposed to realize this technique, including a lead-lag phase detector (LLPD) and a tri-level resistor digital-to-analog converter (TRDAC) for feedback. It distinguishes the leading and lagging phases in an N-stage dual-VCO quantizer so that the resolution increases from log2(N+1) bits to log2(2 ​N ​+ ​1) bits. The TRDAC is also used as biasing DAC and suppresses the process variation. Taking the digital-like analog/mixed-signal design flow, the proposed ADC is implemented in 28-nm CMOS technology occupying only 0.0039 ​mm2. The simulation results show that it consumes 0.552 ​mW ​at a 0.9-V power supply, and achieves a 66.9-dB signal-to-noise-and-distortion ratio (SNDR) at 900 ​MS/s over 6-MHz bandwidth. With a similar SNDR to prior works, this technique lowers the Figure-of-Merit (FoM) to 25.5 fJ/conv.-step.

A 5.2-Mpixel 88.4-dB DR 12-in CMOS X-Ray Detector With 16-bit Column-Parallel Continuous-Time Incremental ΔΣ ADCs

This article presents a 5.2-Mpixel, 12-in wafer-scale CMOS X-ray detector that consists of lithographically stitched 169 sub-chips. The detector employs a 3T pixel with a voltage-controlled storage capacitor to achieve both a low dark random noise (RN) and a large well capacity, and the pixel outputs are read out by column-parallel continuous-time (CT) incremental delta-sigma (ΔΣ) analog-to-digital converters (ADCs). The use of a CT incremental ΔΣ ADC enables high resolution and low energy consumption while securing uniformity and robustness over the 12-in wafer. This work is fabricated in a 1P4M 65-nm CMOS technology. The 16-bit ADC implemented within a 45-μm pitch achieves a differential nonlinearity (DNL) of +0.79/-0.65 LSB, an integral nonlinearity (INL) of +6.85/-6.15 LSB, and a peak signal-to-noise ratio (SNR) of 88.5 dB with a conversion time of 12.6 μs. This detector achieves a CFPN of 181 μV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rms</sub> , a dark RN of 267 μV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rms</sub> , and a DR of 88.4 dB while consuming 3.9 W at 30 frames/s. Compared with the state of the arts, this work achieves 3× larger spatial resolution, 1.8× higher pixel rate, 1.9× higher energy-efficiency, and 17 dB higher DR, simultaneously.

A 0.029-mm2 17-fJ/Conversion-Step Third-Order CT &lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;$\Delta\Sigma$ &lt;/tex-math&gt; &lt;/inline-formula&gt; ADC With a Single OTA and Second-Order Noise-Shaping SAR Quantizer

This paper presents a compact and power efficient third-order continuous-time (CT) delta-sigma (ΔΣ) analog-to-digital converter (ADC) with a single operational transconductance amplifier (OTA). A 4-bit second-order fully passive noise-shaping (NS) successive-approximation-register (SAR) ADC is employed as the quantizer while inherently provides two additional NS orders. Fabricated in 40-nm CMOS, the prototype occupies 0.029 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> of active area and consumes 1.16 mW of power when clocked at 500-MHz sampling frequency. The proposed CT ΔΣ ADC achieves a peak signal-to-noise-and-distortion ratio (SNDR) of 70.4 dB over 12.5-MHz bandwidth, yielding a Walden figure of merit (FoM) of 17 fJ/conversion-step.

Mixed-Signal Hardware Security: Attacks and Countermeasures for ΔΣ ADC

Mixed-signal integrated circuits (ICs) play an eminent and critical role in design and development of the embedded systems leveraged within smart weapons and military systems. These ICs can be a golden target for adversaries to compromise in order to function maliciously. In this work, we study the security aspects of a tunnel field effect transistor (TFET)-based first-order one-bit delta-sigma ( Δ Σ ) analog to digital converter (ADC) through proposing four attack and one defense models. The first attack manipulates the input signal to the Δ Σ modulator. The second attack manipulates the analog version of the modulator output bit and is triggered by the noise signal. The third attack manipulates the modulator output bit and has a controllable trigger mechanism. The fourth attack manipulates the analog version of the modulator output bit and is triggered by a victim capacitance within the chip. For the defense, a number of signal processing filters are used in order to purge the analog version of the modulator output bit for elimination of the malicious unwanted features, introduced by the attacks. According to the simulation results, the second threat model displays the strongest attack. Derived from the countermeasure evaluation, the best filter to confront the threat models is the robust regression using the least absolute residual computing method.

A simple circuit technique to relax the feedback timing of ΔΣ ADC for high-speed and high-accuracy applications

A novel and simple circuit technique to relax the feedback timing of input feed-forward ΔΣ analog-to-digital converter (ADC) is proposed for wideband and high-accuracy applications. The proposed method allows the use of low-speed comparator and DEM logic even for high-speed operation which helps to reduce the power consumption. A delta-sigma ADC with relaxed feedback timing was designed and simulated. The results verify the advantages of the proposed technique.

Improved double noise coupling ΔΣ analog-to-digital converter

In Jung et al. (Electron Lett 48(10):557---558, 1), a double noise coupling scheme was proposed for ΔΣ analog-to-digital converters (ADCs) to achieve wideband and high accuracy performance combined with low power consumption. In this paper, an improved version of double noise coupling ΔΣ ADC is presented. The improved architecture reduces the power consumption significantly, by reducing the output swing of the second integrator in the modulator. Also, the improved double noise coupling ΔΣ ADC relaxes the feedback timing of the modulator using a triple sampling technique (Kanazawa et al. in IEEE Custom Integrated Circuit Conference, 2). Thus, there is no need to have high-speed comparator and DEM circuitry even for high-speed applications. By using both techniques, the performance of the double noise coupling ΔΣ ADC can be improved significantly.

A 10.2 mW multi-mode continuous-time ΔΣ ADC with 70–87 dB DR and 0.7–10 MHz bandwidth for TD-SCDMA and LTE digital receivers

This paper presents a low power and area-efficient 3rd-order continuous-time delta-sigma (CT ΔΣ) modulator for LTE/TD-SCDMA digital receivers. In the proposed modulator, the integrators' coefficients are programmable to meet all LTE and TD-SCDMA signal bandwidths and dynamic range requirements. Moreover, to meet both the high performance and low-cost requirements, the proposed analog-to-digital converter (ADC) adopts: a low-cost excess loop delay compensation method, a non-return-to-zero feedback digital-to-analog converter (DAC) which is clocked by low-noise LC phase lock loop, an on-chip tuning scheme to reduce sensitivity to bandwidth variations, and dynamic element matching 9-level DACs. The CT ΔΣ modulator is designed and fabricated in a 0.13 μm 1-poly 6-metal standard CMOS technology and occupies an active area of 0.20 mm2. For all signal bandwidths of LTE/TD-SCDMA standards, the proposed ADC achieves 70---87 dB dynamic range, and 66---84 dB peak SNDR with 8.4---10.2 mW power consumption under 1.5 V power supply.

A 70.7-dB SNDR 100-kS/s 14-b SAR ADC with attenuation capacitance calibration in 0.35-µm CMOS

In sensor applications, low-power and moderate-high resolution analog-to-digital converters (ADCs) are needed to convert the analog front-end signal output. Such systems are often multi-channel and require analog multiplexing. In these cases, even when high resolutions are required, continuous time $$\varDelta \varSigma $$ΔΣ ADCs can't be adopted, and an efficient data-conversion must be achieved relying on different topologies, typically successive approximation-register (SAR) ADCs. Since these systems are often implemented in CMOS processes like 250- and 350-nm CMOS to benefit from a large supply voltage, the SAR ADC design is challenging due to the technology mismatch and to the limited number of metals available to optimize the layout. This paper presents a SAR ADC implemented in 350-nm CMOS technology with a physical resolution of 14 bits using a binary weighted with attenuation capacitor array. The proposed converter exploits a semi-custom and isotropic unit capacitance with ground shield to avoid proximity effects and parasitic capacitances across its terminals, an optimized capacitive array layout insensitive to both linear and radial oxide gradients, and an efficient calibration algorithm to compensate the parasitic capacitances that worsen the converter linearity. At 1.8-V supply and 100-kSps sampling frequency, the proposed ADC achieves an SNDR of 70.7 dB, an SFDR of 81.8 dB, an ENoB of 11.45 and a power consumption of $$43.4\,\upmu \hbox {W}$$43.4μW, corresponding to a figure-of-merit (FoM) of 155 fJ/conv.step. To the best of our knowledge, this figure is the best among SAR converters implemented in 350-nm or less scaled technologies, and in-line with other ADCs featuring an SNDR larger than 70 dB.

A Fully Integrated BIST &lt;inline-formula&gt; &lt;tex-math notation="TeX"&gt;\(\Delta \Sigma \) &lt;/tex-math&gt;&lt;/inline-formula&gt; ADC Using the In-Phase and Quadrature Waves Fitting Procedure

This paper demonstrates a fully integrated builtin self-test (BIST) ΔΣ analog-to-digital converter (ADC) based on the proposed in-phase and quadrature waves fitting (IQWF) procedure. The IQWF procedure enables accurately measuring the phases and amplitudes of test responses so as to enhance the test accuracy of the BIST circuitry. The all-digital BIST circuitry, with on-chip stimulus generator and response analyzer, conducts single-tone functional tests to test for the ADCs characterization results such as signal-to-noise-and-distortion ratio (SNDR), dynamic range (DR), frequency response, input-referred offset, and gain error. Since the IQWF procedure is performed successively in real time, the BIST circuitry does not need huge memory to store all the output samples like conventional fast Fourier transform (FFT) analysis does. The overall hardware overhead only consists of 16.6 k digital gates. The fully integrated BIST ΔΣ ADC has been fabricated in 0.18-μm CMOS. Measurement results show that the BIST circuitry reports a peak SNDR of 88.0 dB and a DR of 92.6 dB while the corresponding FFT-based analog tests result in 88.8 and 94.1 dB, respectively. Particularly, the BIST circuitry achieves a test bandwidth as wide as the ADCs 20-kHz rated bandwidth, which is the widest to the best of our knowledge. The proposed BIST ADC can be tested without costly external test resources and is thus well suited for the applications in which conventional test resources are not available such as 3-D ICs.

Blind Calibration Algorithm for Nonlinearity Correction Based on Selective Sampling

This paper proposes a blind calibration algorithm for suppressing nonlinearity in analog-to-digital converters (ADCs). The proposed algorithm does not need any external calibration signal and is first of its kind. The proposed algorithm relies on the properties of downsampling and orthogonality of sinusoidal signals to estimate the nonlinearity coefficients present in the system and can be operated to remove even and odd order nonlinearities simultaneously. The working of the algorithm is demonstrated on a first-order ring oscillator based ΔΣ ADC, whose performance is limited due to the nonlinearity present in its system. Built in 0.13 μm CMOS, the algorithm improves the SNDR of the ADC by 39 dB, while improving SFDR by 45 dB.

A Time-Domain High-Order MASH $\Delta\Sigma$ ADC Using Voltage-Controlled Gated-Ring Oscillator

In this paper, a time-domain high-order ΔΣ analog-to-digital converter (ADC) using voltage-controlled gated-ring oscillator (VC-GRO) and time-domain multi-stage-noise-shaping (MASH) is introduced. To implement the high-order noise transfer function (NTF), a voltage-controlled oscillator (VCO) and VC-GRO quantizers are cascaded. Unlike conventional high-order ΔΣ ADC using feedback loop, the proposed ADC has advantages that the architecture is open-loop and the quantizer resolution depends on the time resolution, thus making it attractive for deep submicron CMOS process. The performance of the proposed ADC is theoretically analyzed and simulated, including non-ideal conditions such as nonlinearity, mismatch, propagation delay of logic gates, phase noise, and sampling clock jitter.