Dry Etching Research Articles

Boron-doped amorphous carbon deposited by DC sputtering for a hardmask: Microstructure and dry etching properties

Boron-doped amorphous carbon (a-C) films have been investigated as a hardmask material for improving semiconductor integration, deposited using direct current (DC) magnetron sputtering with varying boron concentrations. Increased boron doping concentration in a-C led to a higher etch resistance but also resulted in the gradation of etch resistivity in the depth direction of the film, as confirmed by a continuous dry etching process. Scanning transmission electron microscopy electron energy loss spectroscopy showed an increase in the sp3 ratio of the film owing to boron doping as well as gradation in the B K edge region of a film doped with a high concentration of boron. This is because the high reactivity between boron and oxygen results in the reaction of residual oxygen in the chamber with boron. Time-of-flight secondary ion mass spectrometry was used to evaluate the penetration resistance to fluorine ions in the dielectric etchant. The results confirmed that B-O bonding resulted in relatively low fluorine resistance. Boron bonded with carbon can significantly improve the dry etch performance; however, bonding with oxygen needs to be effectively controlled to realize desirable film properties. Overall, this study demonstrates the potential of boron-doped a-C films as a hardmask material for the semiconductor industry.

Improvement in quantum efficiency of green GaN-based micro-LED by trapezoidal quantum well

The main challenges in the application of GaN-based full-color micro-light-emitting diodes (micro-LEDs) are size-dependent effects and low quantum efficiency, especially for green micro-LEDs. In this study, we propose to use a trapezoidal quantum well (QW) structure in GaN-based green micro-LEDs. The trapezoidal QW structure is able to improve the electron hole wave function overlap, thus increasing the external quantum efficiency (EQE). Green micro-LEDs with active region size of 75 × 64 μm2 are fabricated by metal organic chemical vapor deposition. The peak EQE of the green trapezoidal QW micro-LED reaches 15.8% at a low injection current density of 0.6A/cm2, which is 1.96 times higher than that of conventional rectangular QW. The test results indicate that the trapezoidal QW structure greatly improves the quantum efficiency of green micro-LED, inhibits the blue shift of peak wavelength and improves color purity, which paves the way to single substrate full-color micro-LED display with high-performance. The technology proposed in this paper does not change the production line equipment, but improves the traditional process, so it is expected to significantly improve the external quantum efficiency of the existing green micro-LED under the existing equipment. The production technology of existing InGaN QW micro-LED is directly adopted, and the EQE can be further improved if some new dry etching and passivation methods are applied.

Fabrication of infrared detector with monolithic microlens produced in thermal reflow process

We report fabrication of monolithic GaAs immersion lens with a sub-milimeter diameter for InAsSb infrared detectors. The microlenses were produced by thermal reflow process of cylindrical photoresist structures, followed by dry etching. The implementation of microlens leads to an increase in the optical area of the photodetector, while maintaining the electrical area dimensions. Detectors with microlenses exhibit three times higher normalized detectivity D* than flat detectors, while conserving a similar level of resistance and current sensitivity. This result proves that the processes related to lens formation do not result in degradation of the photosensitive structure.

High quality GaN microplatelets grown by metal-organic vapor phase epitaxy on patterned silicon-on-insulator substrates: Toward micro light-emitting diodes

In this paper, we report the use of three pendeo-epitaxy growth approaches as a way of reducing the threading dislocation density (TDD) of 20 × 20 μm2 GaN platelets to be used for the development of micro light-emitting diodes (μLEDs). The method relies on the coalescence of GaN crystallites grown on top of a network of deformable pillars etched into a silicon-on-insulator substrate. Our approach takes advantage of the creeping properties of SiO2 at the usual GaN epitaxial growth temperature, allowing the GaN crystallites to align and reduce the grain boundary dislocations. Furthermore, this bottom-up approach allows to get rid of the dry plasma etching step for μLEDs fabrication, which highly deteriorates sidewalls, reducing the efficiency of future displays. By optimizing the growth conditions and inducing asymmetric nucleation, a TDD of 2.5 × 108 cm−2 has been achieved on the GaN platelets, while keeping a smooth surface.

Effect of Large-Area Exfoliation and Etching on the Electrical Behavior of Transition-Metal Dichalcogenide Field-Effect Transistors

Large-area layer transfer was used to fabricate multilayer transition-metal dichalcogenide (TMDC) thin-film transistor (TFT) arrays with areas of (40 × 40 μm2) from single-crystal flakes. The effects of plasma etching of the TFT backchannel surface and bulk defects in the layers on the electrical performance and stability of the n-channel depletion-mode TFTs were investigated. Few-layer structures (∼3 monolayers) were fabricated using a dry etching process to thin multilayer (∼60–90 nm thick) TMDC structures. The etching improved the threshold voltage of the TFTs, resulting in a positive threshold voltage shift of +40 V after etching the backchannel, correlating to a bulk trap density of approximately 1 × 1016 cm–3 eV–1 per monolayer. Etching the MoS2 surface resulted in a threshold voltage shift of 0.2 V per nanometer of MoS2 removed (for MoS2 thicknesses >15 nm). For MoS2 layers etched to <15 nm, the threshold voltage changed to ∼1.8 V per nanometer. An observed degradation of the carrier transport and electrical stability of these samples were found to be due to the proximity of the etched surface approaching the active channel region of the device. The results reveal the performance trade-offs of fabricating large-area arrays of few-layer TMDC TFTs using a mechanical exfoliation and dry etching approach.

Design and Manufacture of Polarization-Independent 3D SOI Vertical Optical Coupler.

An optical coupler is a key input/output (I/O) device in a photonic integrated circuit (PIC), which plays the role of light-source import and modulated light output. In this research, a vertical optical coupler consisting of a concave mirror and a half-cone edge taper was designed. We optimized the structure of mirror curvature and taper through finite-difference-time-domain (FDTD) and ZEMAX simulation to achieve mode matching between SMF (single-mode fiber) and the optical coupler. The device was fabricated via laser-direct-writing 3D lithography, dry etching and deposition on a 3.5 µm silicon-on-insulator (SOI) platform. The test results show that the overall loss of the coupler and its connected waveguide at 1550 nm was 1.11 dB in transverse-electric (TE) mode and 2.25 dB in transverse-magnetic (TM) mode.

Fabrication of 4H-SiC piezoresistive pressure sensor for high temperature using an integrated femtosecond laser-assisted plasma etching method

The processing, particularly, etching of brittle, hard, and anti-corrosion materials represented by the third-generation wide bandgap semiconductor silicon carbide (SiC), is a significant challenge. Although SiC has excellent electrical, mechanical, and chemical properties, the difficulty of processing limits its application in various sensor devices. To solve this problem, in this study, an integrated processing method of femtosecond laser-assisted SiC dry etching is proposed, which realizes high surface quality and high rate etching of the SiC microstructure. Specifically, the effects of different laser processing parameters on the processing effect were first studied through orthogonal experiments. Experiments indicate that compared with laser power and laser scan times, laser processing speed has a more obvious impact on the processing effect. Subsequently, considering the elastic modulus anisotropy of SiC, a 5 MPa piezoresistive pressure sensor chip was designed. Using the proposed composite processing method, a chip sensitive diaphragm was obtained. The diaphragm thickness and diameter are 76 μm and 1700 μm respectively. The overall sensor chip dimension was 4000 μm × 4000 μm × 350 μm. Static tests demonstrated that the sensor have excellent performance with sensitivity of 6.8 mV/MPa, linearity of 0.69% FS, and repeatability of 0.078% FS. In addition, by designing high-temperature packaging, the sensor achieved a pressure test at 400 °C. This study verifies the feasibility of the composite processing method, realizes the fabrication and measurement of high-temperature pressure sensors, and provides a reference for the micro-and nanostructure processing of various SiC sensors.

On the origin and evolution of hotspots in multipatterning processes

Understanding the origins and propagation of defects and hotspots in patterning processes used for semiconductor fabrication is of paramount importance in managing yield. In this paper, results from physics-based simulators to model lithography and dry etch processes are presented and compared to experimental results. These models are used to study different types of hotspots and defects observed in a litho-etch-litho-etch (LELE) multipatterning process. At each pass of the LELE flow, patterns are printed into a SiO2 collecting layer using a trilayer film stack comprised of a negative tone photoresist layer, a spin-on-glass layer (SOG), and a spin-on-carbon layer (SOC). After both passes of the LELE process, the patterns in the SiO2 collecting layer will be transferred to a TiN hardmask prior to final etch into an underlying dielectric. The SOG and SiO2 layers are etched using fluorocarbon plasma, while the SOC layer is etched with an H2/N2 plasma generated in a capacitively coupled plasma source. A pinching hotspot is observed during the single litho-etch pass in a region where two features are placed very close and the image contrast is low. However, for some lithography process conditions, this hotspot is rectified by subsequent etch steps and does not always transfer as a defect into the SiO2 layer. The quenching of the hotspot occurs primarily during the etching of the SOC layer due to the aspect ratio-dependent etching (ARDE) effect. A bridging hotspot is also observed at lithography during the single litho-etch pass at high exposure doses. This hotspot, on the other hand, is exacerbated by the etch steps because of the ARDE effect. Hotspots are also identified that originate from overlay errors between photomasks exposed during first and second passes of the LELE process. The etch bias generated during etching of the SOG layer is crucial to ensure that the overlay-related hotspot does not translate to the SiO2 layer. The extent of etch bias in the SOG etch step is critical and can be tuned by adjusting the neutral to ion flux ratio during that etch step. Increasing the flux ratio improves the process window for the overlay defect; however, when the ratio is higher than approximately 20% of the nominal value, a different defect type is formed in the SOG layer due to the inverse ARDE effect that propagates downstream to the SiO2 layer.

Biomimetic moth-eye nanostructures fabricated by nanosphere lithography in ZnSe enhancing transmission in the mid-infrared

ZnSe is a highly regarded material for optical windows in the infrared spectrum, where transmission efficiency is a critical factor. Traditional surface antireflective coatings have limitations that can be overcome with biomimetic moth-eye nanostructures. In this paper, we present a novel method using nanosphere lithography with polystyrene (PS) nanosphere to fabricate moth-eye nanostructures (MENS) on ZnSe surface with an exceptional antireflection effect. The parabolic profile MENS, which is challenging to fabricate through conventional methods, was directly obtained using our dry etch process. This profile outperformed other shapes like circular cones, resulting in better antireflective performance. Our experimental results matched perfectly with the modeling and demonstrated that the MENS had broadband antireflection performance in the 2–5 μm wavelength range. The maximum transmission of MENS was 82.6%, which was a significant improvement over the flat ZnSe with 71.28% transmission, achieving a 17.2% transmittance enhancement that is close to the ZnSe transmission limit. Moreover, the MENS exhibited a highly desirable hydrophobicity with a wetting angle of 114° instead of 71° on flat ZnSe. Our work displays great potential in optoelectronic devices and high-power laser applications.

P‐40: TFT‐LCD a‐Si Wet Etch Technology

In this paper, we investigate a technology to change the method and principle of n+ a‐Si:H etching from conventional dry etch to the innovative wet etch in TFT LCD fabrication. The technology is based on the development of a new wet metal etching solution and the design of the thinnest film thickness of a‐Si:H in the industry, combined with the etching process development, to achieve the etching of two different film layers of metal and N+ a‐Si:H in the back channel of TFT switches in one‐ step(Abbreviated as NW process). The process can effectively improve the capacity of Dry Etch process (Skip N+ Dry Etch); improve the uniformity of back channel a‐Si:H Remain (16.3%‐ &gt;7.6% ); improve product characteristics (Dark I on（ TFT working current） 5.5‐&gt;6.0); improve yield (Yield rate↑0.3%).The process has been successfully developed for the first time in Wuhan BOE and has been widely used for batch products, meanwhile, the process has been extended to Hefei BOE and Fuzhou BOE, and other BOE line sites are also actively exploring the experiment.

51‐3: Copper Thin Film Dry Etching Equipment via ECR Plasma Source

This paper presents Gen. 2 (370 mm * 470 mm) size thin copper film dry etching performance that is etched by high electron temperature plasma source with low temperature substrate. Dry etching is performed using HCl gas in a reactive ion etching mode. In addition, scanning low temperature susceptor and the electron cyclotron resonance (ECR) plasma produced by rectangular‐type microwave slot antenna (ReSLAN) are used.

All‐Glass Metasurfaces for Ultra‐Broadband and Large Acceptance Angle Antireflectivity: from Ultraviolet to Mid‐Infrared (Advanced Optical Materials 12/2023)

In article number 2300137, Nathan J. Ray, Jae-Hyuck Yoo, Hoang T. Nguyen, and Eyal Feigenbaum demonstrate the ability to generate all-glass metasurfaces that exhibit negligible reflection across the broad wavelength band 350 nm (ultraviolet) to 2350 nm (mid-infrared), i.e., virtually the entire solar spectrum for both polarizations and for acceptance angles up to 100° (angle of incidence = ±50°). This is done by dry etching through advanced nanoparticle etching masks, yielding unprecedented aspect ratios of the resultant metasurface nanofeatures. Among the vast application-space available for these structures, the results have great potential for fabrication of cover glass for solar cells, frequency-converted laser systems, and additive manufacturing.

75‐3: Investigation of Influence and Improvement of Dry Etch on Glass Strength

None film surface of TFT glass will be damaged varying degrees due to physical contact with array equipment, which will seriously reduce the strength of none film surface. In this paper, we clarified the physical damage caused by the dry etch equipment on none film surface of TFT and its impact on the strength reduction through multiple verifications in array process. It is proved that strength reduction is mainly related to the back electrode material of dry etch. By changing the back electrode material from M to N(code name), the strength of the acrylic ball drop increased by more than 500%, and the strength of the cell ROR increased by 57%. This research has greatly improved the strength of none film surface of LCD, which is great significant to product performance improvement and new product certification.

74‐3: Inkjet‐Printed High‐Performance Organic Thin‐Film Transistors

We describe organic thin‐film transistor (OTFT) demonstration by integrating existing photolithographic technology with inkjet printing, eliminating the need for dry etching and significantly reducing material consumption and the number of manufacturing processes, making OTFTs suitable for mass production. OTFTs fabricated this way demonstrate performance superior to that of amorphous silicon.

Selective Wet and Dry Etching of NiO over β-Ga2O3

Patterning of NiO/Ga2O3 heterojunctions requires the development of selective wet and dry etch processes. Solutions of 1:4 HNO3 :H2O exhibited measurable etch rates for NiO above 40 °C and activation energy for wet etching of 172.9 kJ.mol-1 (41.3 kCal.mol-1, 1.8 eV/atom), which is firmly in the reaction-limited regime. The selectivity over β-Ga2O3 was infinite for temperatures up to 55°C. The strong negative enthalpy for producing the etch product Ga(OH)4 suggests that HNO3-based wet etching of NiO occurs via the formation and dissolution of hydroxides. For dry etching, Cl2/Ar Inductively Coupled Plasmas produced etch rates for NiO up to 800Å.min-1, with maximum selectivities of < 1 over β-Ga2O3. The ion energy threshold for initiation of the etching of NiO was ~55 eV and the etch mechanism was ion-driven, as determined by the linear dependence of etch rate on the square root of ion energy incident on the surface.

(Invited) Fabrication and Device Performance of 2.7 Kv/2.5A NiO/Ga2O3 Heterojunction Power Rectifiers

The fabrication and switching characteristics of large diameter (1mm) Ga2O3 heterojunction rectifiers with bilayers of NiO as the p-type layer are reported. The band alignment shows this is a staggered-gap system. Selective wet and dry etching was developed to allow fabrication of vertical geometry heterojunction rectifiers. A forward current of 2.5 Amperes was achieved, with a reverse breakdown voltage of 2.7 kilovolts. The on/off ratio was above 108 over a broad range of switching voltages, with a measurement-limited reverse recovery time of 100 nanoseconds.

Enhanced Device Performance with Vertical SiC Gate-All-Around Nanowire Power MOSFETs

SiC gate-all-around (GAA) nanowire (NW) MOSFET is one of the most promising device architectures for the next generation of SiC power MOSFETs. This work reveals the great application potential of vertical SiC GAA NW power MOSFETs via TCAD simulation. The investigated devices show higher channel electron mobility (µch) and larger channel carrier density (nch) compared to the conventional SiC power MOSFET. Scaling down of NW diameter (DNW) is beneficial in terms of both, lowering channel resistance (Rch) via improving nch and, increasing breakdown voltage (Vb) by modifying electric field distribution. Low specific-on resistance (Ron,sp) of about 0.68 mΩ∙cm2 for 1 kV SiC MOSFET is shown as possible. However, scaling down the DNW below 100 nm causes an undesirable increase in Ron,sp due to the unscalable device area which is limited by the vertical gate wrapping stacks. The study on device scaling where the NW diameter (DNW) varies from 500 nm to 25 nm provides valuable design considerations for the device's performance. Finally, a top-down process has been developed for the device fabrication. Vertical SiC NWs with an aspect ratio of 10 are formed by an optimized micro-trench free dry etching process.

Ion energy dependence of dry etch damage depth in Ga2O3 Schottky rectifiers

The β-polytype of Ga2O3 has a high critical electric field strength (∼8 MV.cm−1) and can be grown as large diameter (6 in.) single crystal boules by inexpensive melt-growth techniques. This makes it promising for next generation power electronics and solar-blind UV photodetectors. Since wet etching is not feasible for patterning such devices due to the chemical inertness of Ga2O3, attention is focused on dry etching, with the attendant issue of surface modification due to chemical or ion-induced changes. In this work, we demonstrate that dry etch damage in β-Ga2O3 is manifested by a reduction in near-surface carrier concentration, possibly due to the introduction of Gav acceptor states. The depth to which the carrier density is affected depends on the interplay between ion energy and etch rate, with faster etch rates reducing the depth of the remaining damaged region. The maximum damage depth observed experimentally from capacitance-voltage profiling on Schottky rectifiers was ∼ 110 nm, well beyond the range of the ions in the Inductively Coupled Plasmas and emphasizing that rapid diffusion of point defects occurs into the sample during the etch step. Using Schottky rectifier structures as a platform to understand the effect of dry etch damage on device parameters, we found that on-state resistance was more affected than ideality factor or breakdown voltage, with a large increase (5x) for ion energies ≥ 325 eV. Reverse current density characteristics showed the presence of trap-assisted space-charge-limited conduction in the damaged layers. The implications for high power rectifier fabrication are discussed.

Dielectric Metalens by Multilayer Nanoimprint Lithography and Solution Phase Epitaxy

Metasurfaces have ushered in a huge development for their superior ability in manipulating light properties including phase, amplitude, and polarization, which show great potential as alternatives for the refractive optical devices. Recently, many applications of metasurface including metalens have been proposed and investigated, aiming at substituting their refractive counterparts. However, the commonly used fabrication approaches employ electron‐beam lithography (EBL) followed by dry etching or atomic layer deposition (ALD) of dielectric materials, which are expensive and inefficient. Besides, dry etching of dielectric materials at sub‐100 nm scale with a high aspect ratio is challenging. Herein, a new approach for dielectric metalens fabrication is presented, which combines multilayer nanoimprint lithography and solution phase epitaxy. High aspect ratio ZnO nanopillars with a height‐to‐diameter ratio of over 7:1 are demonstrated. By using the multilayer nanoimprint lithography, increased aspect ratio nanostructures from shallow imprinting molds are obtained. The highly anisotropic growth characteristic enables nanopillars to grow at a height that exceeds the resist thickness. With this ability, ZnO metalenses are fabricated where the height of nanopillar reaches 1.1 μm, achieving a focusing efficiency of 50%. The process is cost‐effective with a high throughput, which can be widely used for many optical applications.

A Dry Etch Approach To Reduce Roughness and Eliminate Visible Grind Marks in Silicon Wafers Post Back-Grind

3D wafer packaging represents a significant component of the total wafer level processing cost. Replacement of the Chemical Mechanical Polishing (CMP) process step with a corresponding dry etch can yield significant time and cost savings. Incorporating equipment already utilized in the 3D integrated wafer packaging process during the subsequent Through Silicon Via (TSV) reveal step, process efficiencies can be achieved, with overall die yields being maintained. Using dry etch technology to treat a 200nm rough back-ground silicon surface, a smooth surface with a peak to valley roughness of less than 6nm is demonstrated. This patented process differs from other dry etch smoothing techniques in that it aims to eliminate any visual grind marks rather than just reducing the surface roughness. The elimination of visible grind marks is critical in later optical inspection where they are falsely identified as defects. The quality of the surface is equivalent to that of a CMP processed wafer and as such, this process has been implemented in manufacturing replacing the CMP step. The novel process described combines a surface modification followed by a roughness reduction in an iterative manner to produce a smooth surface without visible grind marks post processing.