Enhanced Device Performance with Vertical SiC Gate-All-Around Nanowire Power MOSFETs

Abstract

SiC gate-all-around (GAA) nanowire (NW) MOSFET is one of the most promising device architectures for the next generation of SiC power MOSFETs. This work reveals the great application potential of vertical SiC GAA NW power MOSFETs via TCAD simulation. The investigated devices show higher channel electron mobility (µch) and larger channel carrier density (nch) compared to the conventional SiC power MOSFET. Scaling down of NW diameter (DNW) is beneficial in terms of both, lowering channel resistance (Rch) via improving nch and, increasing breakdown voltage (Vb) by modifying electric field distribution. Low specific-on resistance (Ron,sp) of about 0.68 mΩ∙cm2 for 1 kV SiC MOSFET is shown as possible. However, scaling down the DNW below 100 nm causes an undesirable increase in Ron,sp due to the unscalable device area which is limited by the vertical gate wrapping stacks. The study on device scaling where the NW diameter (DNW) varies from 500 nm to 25 nm provides valuable design considerations for the device's performance. Finally, a top-down process has been developed for the device fabrication. Vertical SiC NWs with an aspect ratio of 10 are formed by an optimized micro-trench free dry etching process.