Vertical nanowire InGaAs MOSFETs fabricated by a top-down approach

Abstract

Vertical In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.53</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.47</sub> As Gate-all around (GAA) nanowire (NW) MOSFETs fabricated by a top-down approach are demonstrated experimentally for the first time. The fabrication process features a new III-V dry etch process capable of sub-20 nm diameter NWs with an aspect ratio greater than 10. It also includes a digital etch technique to controllably reduce nanowire diameter and remove dry etch damage. With a channel length L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ch</sub> =80 nm and EOT=2.2 nm, we obtain a transconductance of 730 μS/μm at 0.5 V in a 50 nm diameter NW MOSFET. The digital etch increases the transconductance by 20% and improves the subthreshold characteristics of the devices. In terms of balance of transport and short-channel effects, our MOSFETs match the best vertical nanowire devices fabricated by bottom-up techniques.