A Superjunction U-MOSFET With SIPOS Pillar Breaking Superjunction Silicon Limit by TCAD Simulation Study

Abstract

A novel superjunction (SJ) vertical UMOSFET with semi-insulating POly-crystalline silicon pillar (SIPOS SJ-UMOS) is proposed and its mechanism is investigated by TCAD simulations. In the off-state, the reshape effect of SIPOS pillars enhances the vertical electric field strength and weakens the lateral field component, which increases the breakdown voltage (BV). In addition, the highly doped $N$ -pillars are allowed for the proposed device due to the enhanced depletion by the SIPOS pillars, which leads to a low specific ON resistance ( ${R}_{{\text {ON},\text {sp}}}$ ). In the on-state, an accumulation layer is formed in drift region leading to an additional reduction in the ${R}_{{\text {ON},\text {sp}}}$ . Simulation results show that the $\text {R}_{{\text {ON},\textit {sp}}}$ decreases 59%, and BV increases by 16.7%, simultaneously, breaking the SJ silicon limit, compared with those of a conventional SJ-UMOS with the same drift length. Moreover, the charge-imbalance endurance of SIPOS SJ-UMOS is also improved.