(Invited) SiC Lateral Mosfet Implemented on Semi-Insulating Substrate

Abstract

In most cases, lateral SiC MOSFETs implemented on a SiC epitaxial layer which grown on off-axis conducting substrate. For 4H-SiC, 4º-off toward <11-20> substrate is widely used in order to avoid polytype inclusion. However, step bunching often occurs during the epitaxial growth and high temperature activation process. The step bunching makes surface rough and causes scattering of carriers at the surface. Consequently, the channel mobility of the lateral MOSFET implemented on epitaxial layer grown on off-axis substrate is reduced. Therefore, on-axis substrate has advantages for improving static characteristics compared to the off-axis substrate. However, it is still possible to create polytype inclusion on an on-axis substrate during epitaxial growth, and elimination of epitaxial layer is preferred in many aspects. In this research, 4H-SiC lateral double implanted MOSFET (LDIMOSFET) have been designed and fabricated on an on-axis high purity semi-insulating (HPSI) substrate for the first time. To avoid the step bunching and polytype inclusion problem, we used on-axis SiC substrate without epitaxial layer. Figure 1 shows a cross-sectional view of the LDIMOSFET. As shown in the figure, proposed LDIMOSFET adopted a current path layer (CPL) instead of an epi-layer of the conventional lateral MOSFET. All regions of the LDIMOSFET were formed by ion-implantation. The CPL region plays an important role in obtaining MOSFET characteristics. At a forward bias condition, the CPL serves as a current path of the device, and at reverse bias condition, it serves to support the breakdown voltage. Without CPL region, only the semi-insulating layer exists between the p-base and n+ drain region. In this case, due to a low concentration of the semi-insulating substrate, small value of forward current will flow. Therefore, for obtaining desired forward and reverse characteristics, it is important to optimize the CPL parameters such as doping concentration (NCPL), depth (DCPL), and length (LCPL). To optimize the CPL parameters, device simulations were performed by using device simulator Silvaco-ATLAS. In order to obtain high breakdown voltage and low specific on-resistance, NCPL and DCPL should be within range of 2 × 1016 ≤ NCPL ≤ 4 × 1016/cm3 and 0.2 ≤ DCPL ≤ 0.3 μm, respectively. For device fabrication, considering the simulation results, we used NCPL = 2 × 1016 /cm3, and DCPL = 0.3 μm, respectively. Breakdown voltage and specific on-resistance are also depends on LCPL. Therefore, to find out the effect of LCPL on the breakdown voltage and specific on-resistance, LCPL was varied from 5 to 20 μm. For device fabrication, on-axis HPSI 4H-SiC wafers were used. To find out the effect of CPL region on the device characteristics, LDIMOSFET without CPL is also fabricated. The extracted channel mobility of the LDIMOSFET is 21.7 cm2/V∙s. The reported mobility of the Al-implanted MOSFETs fabricated on the on-axis epitaxial layer is 9 to 19 cm2/V∙s, and they explain that the mobility increase is due to the lower surface roughness. We used on-axis HPSI substrate to avoid the surface roughness scattering caused by the step bunching and we observed mobility comparable to those measured in the device implemented on the epitaxial grown on the on-axis wafer. Figure 2 shows measured IDS – VDS characteristics of the LDIMOSFET when LCPL = 5 μm. As shown in the figure, the highest drain current is 22mA/mm. In contrast, currents in the LDIMOSFET without CPL slightly increase when drain voltage exceeds 10 V. A specific on-resistance of the LDIMOSFET is 17.2 mΩ∙cm2 at VG = 25 V and VD = 1 V. When LCPL was increased from 5 to 20 μm, the specific on-resistance of the device also increased, from 17.2 to 89.8 mΩ∙cm2. The breakdown voltage of LDIMOSFET depends on LCPL, DCPL, and NCPL. Figure 3 shows measured breakdown voltage for different LCPL. As shown in the figure, longer LCPL shows higher breakdown voltage, and the maximum breakdown voltage of 1093 V was observed when LCPL = 20 μm. Maximum breakdown voltage of 1093 V was achieved with low specific on-resistance of 89.8 mΩ∙cm2 at LCPL = 20 μm. The figure of merit (BV2/Ron,sp) of the fabricated LDIMOSFET is 13.3 MW/cm2. The breakdown voltage and specific on-resistance of the device can be improved by adopting field plate and RESURF principle. The effect of the field plate and RESURF principle is under investigation. We will discuss about the detailed effects of the field plate, RESURF principle and device parameters on the static characteristics of the fabricated LDIMOSFET at the manuscript. Figure 1