On the Correlation Between Static and Low-Frequency Noise Parameters of Vertical Nanowire nMOSFETs

Abstract

Introduction. The Gate-All-Around (GAA) Nanowire (NW) or nanosheet (NS) architecture provides superior short-channel effects control and is widely considered as one of the most promising candidates to replace finFETs in advanced Logic technology nodes. Compared with their horizontal implementation, vertical NWs (or NSs) FETs [1] offer some clear advantages, appearing promising devices to overcome some of the limitations encountered by conventional CMOS scaling as it reaches its physical limits and faces interconnect routing congestion. They have the potential to yield smaller circuits with reduced power consumption [2], allowing relaxed Lgate without impacting the device footprint. While their fabrication is challenging, several schemes have been proposed for improved process control and device performance [1]. In this work, the static parameters of vertical NW junctionless (JL) nMOSFETs have been studied for devices with two different Replacement Metal Gate (RMG) cap layer widths (see schematics in figure 1), encapsulating the top part of the pillars during processing at the RMG module. It will be shown that this strongly impacts the static device parameters: the threshold voltage (VT), the maximum transconductance (gmmax) and the dynamic output resistance (rout). Moreover, a correlation is shown with the input-referred voltage noise Power Spectral Density (PSD) SVG at 10 Hz, which could be explained in terms of a process-induced variation in the diameter D of the NWs. Experimental. A detailed process description has been recently reported [1]. A 55 nm in situ P-doped n+ layer is deposited by CVD on a low-resistivity silicon substrate (source contact), followed by 90 nm undoped silicon and again 55 nm n+ Si. The RMG stack consists of IL-SiO2/HfO2/TiN/W. An RMG cap consisting of SiO2 is used to encapsulate the top of the pillars. Here, devices with two different cap widths and 100 wires in parallel are compared. On-wafer DC and low-frequency noise measurements have been performed using a BT1500 Parameter Analyzer and an E4727A Advanced Low-Frequency Noise Analyzer from Keysight, respectively. Measurements have been performed in linear operation at a drain voltage VDS=50 mV, while the gate voltage VGS is stepped from weak to strong inversion. Results and Discussion. Figure 1 and 2 compares the linear input ID-VGS characteristics of a set of narrow and wide cap vertical NW nFETs. While there is obvious device-to-device variability, the wide-gap devices (Fig. 2) clearly exhibit a lower VT than their narrow-gap counterparts in Fig. 1. The transconductance (gm) plots of Figs 3 and 4 reveal another trend: devices with a high VT generally exhibit a lower gmmax and vice versa. This is even so within each flavour of devices in Figs 3 and 4. As will be shown, nFETs with a high(er) VT and lower gmmax also tend to exhibit a higher rout. Finally, Figs 5 and 6 demonstrate that the corresponding SVG at f=10 Hz is smaller for the wide-cap devices, especially around VT, where the minimum noise PSD is found. As will be shown, the noise spectra are dominated by 1/f-like noise (f<1 kHz). A possible explanation of the observed parameter variations should provide a consistent picture for the reported correlations. For these particular devices, the NW doping density can be ruled out, as we are studying undoped pillars. The difference in SVG could suggest a difference in oxide/interface trap density, but this is not reflected in the subthreshold swing nor in the PBTI behaviour [1]. On the other hand, it has been reported before that the VT of NW transistors increases for reduce D [3]. This could well explain also the lower gmmax (scales with D) and the higher SVG (scales with 1/D). The different NW diameter could result from the different dummy dielectric removal [1].