Drain Saturation Voltage Research Articles

Pseudo-source gated beta-gallium oxide MOSFET

This study demonstrates pseudo-source-gated beta-gallium oxide (β-Ga2O3) metal oxide semiconductor field effect transistors (MOSFETs). The proposed pseudo-source gated transistor (pseudo-SGT) architecture has a thin (∼11 nm) recessed channel design, effectively emulating conventional SGT characteristics without significantly compromising on-current. The fabricated devices exhibit remarkable intrinsic gain of 104, low output conductance of 10−8 S/mm, transconductance of 10−3 S/mm, and drain saturation voltage of ∼1.5 V, while maintaining a drain current of 1.3 mA/mm. These enhanced performance metrics significantly expand the potential of β-Ga2O3 MOSFETs for the development of Ga2O3 monolithic power integrated circuits.

The Study and Modeling of saturation drain voltage for junctionless FinFET

In this work, the mechanism and model of saturation drain voltage (Vds,sat) for Junctionless FinFET (JLF) are investigated. The Vds,sat of JLF is observed to increase linearly with gate voltage in all operation regions. A physics-based Vds,sat calculation model of JLF is built for fast and simple extraction of saturation drain voltage. The effects on Vds,sat of device parameters such as gate length, Fin height, Fin width and doping concentration, as well as device structure such as top gate and corner of the Fin, are discussed by simulation and model calculation. The results of model meet well with the simulation, and JLF has a low Vds,sat compared with other FinFETs. It shows that JLFs have potential prospect for lower power application in the future.

Fabrication and characterization of GaN-based nanostructure field effect transistors

Two different types of GaN-based nanostructure FETs, such as FinFETs and gate-all-around (GAA) nanowire FETs, have been investigated along with discussing their important performances for a possible new application. The GaN-based FinFETs have better electrostatic control compared to conventional planar-type GaN-based HEMTs, which offers great performance improvement such as very low off-state leakage current, high breakdown voltage, high linearity with broad transconductance. Recent investigation demonstrated that an appropriately designed AlGaN/GaN-FinFETs could exhibit low saturation drain voltage and very fast switching characteristics with subthreshold swing of sub-60 mV dec, which indicates that they can be a promising candidate for low voltage/power logic application. GAA GaN nanowire FETs have even better electrostatic control and exhibit excellent device performances showing their potential low voltage/power logic applications. For clear understanding of the device performances, simulation including two models concerning the multi-level trapping effects and the self-heating effects has been conducted, which leads to good agreement with the experimental results. Negative transconductance and offset-like output characteristics, observed in the narrow nanowire devices, have been well explained using the deep trapping effect and the built-in potential at ohmic contact. Scaling of the nanowire FET has been implemented such as channel length, doping concentration, and diameter of nanowire, which helps to predict further improvement of the device performance.

Investigation Influence of Channel Transport on Output Characteristics in Sub-100nm Heterojunction Tunnel FET

In this paper, the influences of channel transport on the output characteristic in sub-100nm heterojunction tunnel FET have been investigated through TCAD simulation. The calibrated tunneling and transport parameters with experiment have been adopted. The influences of the parameters characterizing channel transport, i.e., mobility, channel length, and saturation velocity, are analyzed in detail under different biases. It is found that the channel transport has stronger impact on the performance of the device biased in the linear region and with smaller mobility, longer channel, and higher saturation velocity. The saturation drain voltage can be reduced by improving the mobility and reducing the saturation velocity. However, the latter will reduce the current simultaneously. What’s more, considering quantum confinement, the variation in performance of the device induced by the change of mobility is still visible after some optimization strategies are used.

Effects of Contact Potential and Sidewall Surface Plane on the Performance of GaN Vertical Nanowire MOSFETs for Low-Voltage Operation

GaN-based materials are expected to show excellent immunity against short-channel effects because they have relatively lower permittivity and higher electron effective mass, compared to other materials such as Si, Ge, and In(Ga)As. To further reduce the short-channel effects, it is important to enhance the gate controllability of the device by utilizing a gate-all-around (GAA) structure. In this article, GaN vertical GAA nanowire MOSFETs with various diameters of 120, 75, and 45 nm have been fabricated. The device with a diameter of 120 nm shows a threshold voltage of 0.7 V, drain saturation voltage of 0.5 V, and subthreshold swing of 70 mV/decade, which would be suitable for low-voltage/power applications. However, the devices with smaller diameters of 75 and 45 nm show peculiar characteristics, such as a second rise of the drain current in output characteristics and a negative transconductance.

P‐6.6: Effects of lightly Doped Drain Structure in n‐channel ELA Bridged‐Grain Poly‐Si TFTs

We lead the lightly doped drain (LDD) structure into the bridged‐grain (BG) poly‐Si thin film transistor (TFT). This combined structure can restrain the gate induced drain leakage current (GIDL) and the electrical characteristics shows not much sacrifice. A high Ion/Ioff current ratio 3.79×108 is achieved. Besides, the device reliability is improved significantly. Because the lateral electrical field decreases by LDD, lower trap state density is generated in the SiO2/poly‐Si interface and the grain boundaries of poly‐Si near the surface conduction channel, resulting in the stable on‐state drive current (Ion) and drain saturation voltage (Vdsat). All test results indicate that the BG poly‐Si TFT with a LDD structure will work well and has a great potential for system‐on‐panel application.

A New Aspect of Saturation Phenomenon in FinFETs and Its Implication on Analog Circuits

This paper presents a physics-based semiempirical model of drain saturation voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS,SAT</sub> ) of a FinFET device suitable for analog circuit design. The previous belief of similarity of the saturation phenomenon in the FinFET and planar MOSFET devices is investigated for the first time and is shown to be inconsistent in the FinFET device. When the value of V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> is increased to V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS,SAT</sub> , then at a critical point, the product of electron density (n) and electron velocity (v <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d</sub> ) starts decreasing at the silicon-dielectric interface while it increases at the mid of the fin. This critical point lies within the drain extension (DE) region near to channel-DE junction. It is also observed that V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS,SAT</sub> increases linearly with V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS,</sub> (≥0.6 V). Based on this, a semiempirical V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS,SAT</sub> model is proposed, which is simple enough to be usable in analog circuit design. Moreover, compared to planar devices, a strikingly different trend of the output resistance (r <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">o</sub> ) in FinFET is observed. We explained this behavior for the first time using our understanding of FinFET saturation phenomenon. By employing our semiempirical model of V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS,SAT</sub> and the trend of r <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">o</sub> with V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> , we estimated the bias voltages of the FinFET amplifier to improve the gain by about 3× while not increasing the power dissipation. Since the gains of cascode and telescopic cascode amplifiers are strongly dependent on r <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">o</sub> , these FinFET amplifiers can be designed to have much smaller overdrive voltages compared to its planar counterparts.

Numerical Investigation of Short-Channel Effects in Negative Capacitance MFIS and MFMIS Transistors: Subthreshold Behavior

In this paper, we analyze the impact of length scaling on the ON-state operation of the two classes of double-gate negative capacitance transistors: metal–ferroelectric–metal–insulator–semiconductor (MFMIS) and metal–ferroelectric–insulator–semiconductor (MFIS). We show that for long-channel structures, MFMIS configuration shows a higher ON current than the MFIS due to a lower drain saturation voltage of the latter. For short-channel cases, we compare these negative capacitance field effect transistors (NCFETs) under two scenarios: equal flat band voltages (iso- ${V}_{\textsf {FB}}$ ) and equal OFF currents (iso- ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ ). In iso- ${V}_{\textsf {FB}}$ condition, a higher negative differential conductance (NDC) effect in the MFMIS suppresses its ON current below that of the MFIS. However, the MFMIS provides a higher ON current than the MFIS for all the channel lengths under iso- ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ condition. We further investigate the influence of quantum mechanical effects and velocity saturation of carriers on the electrical characteristics of short-channel NCFETs. We also explore the impact of inner and outer spacer fringings in NCFETs. We find that the ferroelectric voltage gain in NCFETs with spacers increases with the channel length scaling, which provides a further improvement in the ON current contrary to those without spacers. Moreover, increase in the spacer permittivity also boosts both the ON current and the NDC.

A Novel SOI MESFET to Improve the Equipotential Contour Distributions by Using an Oxide Barrier

A new Metal Semiconductor Field Effect Transistor (MESFET) structure in Silicon on Insulator (SOI) technology will be introduced in this paper. In our idea, an oxide barrier is used on the drain side of the gate to improve DC and AC characteristics of MESFETs. We call the proposed structure as modified equipotential contour MESFET (MEC-MESFET). Our main reason to present this proposed structure is to modify the equipotential contour distributions by using the oxide barrier. In addition, the oxide barrier has a greater energy band gap rather than a silicon (Si) semiconductor. So, in comparison with Si, it will break at higher voltages. The maximum electric field occurs on the gate edge near the drain side in a conventional MESFET (C-MESFET). Therefore, in the proposed structure, by placing an additional oxide barrier in the drain side of the gate and modifying the maximum electrical field in this part, the breakdown voltage increases. The drain saturation and breakdown voltage of the proposed structure improve 21 and 29 percent, respectively, which increases the maximum output power density to 56 percent in comparison with conventional silicon on insulator MESFET (C-MESFET). Moreover, the gate capacitance decreases by using the oxide barrier and consequently improves the frequency characteristics like Unilateral power gain (U), Maximum Available Gain (MAG), current gain (h21), and noise in comparison with the C-MESFET.

Low voltage operation of GaN vertical nanowire MOSFET

GaN gate-all-around (GAA) vertical nanowire MOSFET (VNWMOSFET) with channel length of 300 nm and diameter of 120 nm, the narrowest GaN-based vertical nanowire transistor ever achieved from the top-down approach, was fabricated by utilizing anisotropic side-wall wet etching in TMAH solution and photoresist etch-back process. The VNWMOSFET exhibited output characteristics with very low saturation drain voltage of less than 0.5 V, which is hardly observed from the wide bandgap-based devices. Simulation results indicated that the narrow diameter of the VNWMOSFET with relatively short channel length is responsible for the low voltage operation. The VNWMOSFET also demonstrated normally-off mode with threshold voltage (VTH) of 0.7 V, extremely low leakage current of ∼10−14 A, low drain-induced barrier lowering (DIBL) of 125 mV/V, and subthreshold swing (SS) of 66–122 mV/decade. The GaN GAA VNWMOSFET with narrow channel diameter investigated in this work would be promising for new low voltage logic application.

Bandgap-dependent onset behavior of output characteristics in line-tunneling field-effect transistors

The onset behavior of output characteristics in tunnel field-effect transistors (TFETs) importantly determines the performance of digital TFET-based circuits. In this paper, we analytically and numerically examine the dependence of the onset behavior of output characteristics on the bandgap of semiconductors in line-tunneling TFETs. The qualitative and quantitative analyses show that the output onset behavior in line-tunneling TFETs strongly depends on the bandgap because the roles of two factors, including the incident electron number and tunneling probability, in determining the variation of tunneling current under increasing drain voltage change oppositely when varying the bandgap. Particularly, the superlinear onset in line-tunneling TFETs can be effectively suppressed to reduce the saturation drain voltage by using low-bandgap semiconductors. Together with the advantages in on-current and subthreshold swing as shown previously, the significant superiority in output characteristic makes the use of low-bandgap materials to be an efficient approach for simultaneously enhancing the device and circuit performances of advanced line-tunneling TFETs.

Tunneling contact IGZO TFTs with reduced saturation voltages

We report a tunneling contact indium-gallium-zinc oxide (IGZO) thin film transistor (TFT) with a graphene interlayer technique in this paper. A Schottky junction is realized between a metal and IGZO with a graphene interlayer, leading to a quantum tunneling of the TFT transport in saturation regions. This tunneling contact enables a significant reduction in the saturation drain voltage Vdsat compared to that of the thermionic emission TFTs, which is usually equal to the gate voltage minus their threshold voltages. Measured temperature independences of the subthreshold swing confirm a transition from the thermionic emission to quantum tunneling transports depending on the gate bias voltages in the proposed device. The tunneling contact TFTs with the graphene interlayer have implications to reduce the power consumptions of certain applications such as the active matrix OLED display.

A Novel ${{V}}_{\textsf {DSAT}}$ Extraction Method for Tunnel FETs and Its Implication on Analog Design

This brief investigates for the first time, a method to extract the value of saturation drain voltage for a tunnel FET. The saturation in output characteristics of a TFET is found to take place when the difference in conduction band energy ( $\Delta {\textsf {E}}_{{\textsf {C}}}$ ) of channel ( ${{E}_{\text{CC}}}$ ) and drain ( ${{E}_{\text{CD}}}$ ) is a few ${{K}_{B}}{T}$ . As the drain voltage ( ${{V}_{\text{DS}}}$ ) increases, it is found that the device initially enters in a soft saturation state and subsequently into deep saturation. For any given value of gate voltage ( ${{V}_{\text{GS}}}$ ), the onset of soft and deep saturation happens for a constant difference in ${{V}_{\text{GS}}}$ and ${{V}_{\text{DS}}}$ . We propose a novel method to extract this voltage difference ${{V}_{\text{GD}}}$ , which is explained using a phenomenological approach. We have also validated our results with published experimental data. It is found that the output resistance ( ${{R}_{o}}$ ), transconductance ( ${{g}_{{m}}}$ ), and intrinsic gain ( ${{g}_{{m}}}\times {{R}_{{o}}}$ ) increase when the device enters in a soft saturation and attain a maximum value in deep saturation regime. Furthermore, a common source amplifier biased in soft saturation is also demonstrated to have a comparable voltage gain and bandwidth to the one biased in deep saturation.

Verilog-A implementation of a double-gate junctionless compact model for DC circuit simulations

A physically based model of the double-gate juntionless transistor which is capable of describing accumulation and depletion regions is implemented in Verilog-A in order to perform DC circuit simulations. Analytical description of the difference of potentials between the center and the surface of the silicon layer allows the determination of the mobile charges. Furthermore, mobility degradation, series resistance, as well as threshold voltage roll-off, drain saturation voltage, channel shortening and velocity saturation are also considered. In order to provide this model to all of the community, the implementation of this model is performed in Ngspice, which is a free circuit simulation with an ADMS interface to integrate Verilog-A models. Validation of the model implementation is done through 2D numerical simulations of transistors with and silicon channel length and 1 × 1019 or doping concentration of the silicon layer with 10 and silicon thickness. Good agreement between the numerical simulated behavior and model implementation is obtained, where only eight model parameters are used.

Compact model for short-channel symmetric double-gate junctionless transistors

In this work a compact analytical model for short-channel double-gate junctionless transistor is presented, considering variable mobility and the main short-channel effects as threshold voltage roll-off, series resistance, drain saturation voltage, channel shortening and saturation velocity. The threshold voltage shift and subthreshold slope variation is determined through the minimum value of the potential in the channel. Only eight model parameters are used. The model is physically-based, considers the total charge in the Si layer and the operating conditions in both depletion and accumulation. Model is validated by 2D simulations in ATLAS for channel lengths from 25nm to 500nm and for doping concentrations of 5×1018 and 1×1019cm−3, as well as for Si layer thickness of 10 and 15nm, in order to guarantee normally-off operation of the transistors. The model provides an accurate continuous description of the transistor behavior in all operating regions.

Determination of the Drain Saturation Voltage of a Metal–Oxide–Semiconductor Field-Effect Transistor by the Capacitance–Voltage Method

In this paper, we present a simple technique to extract drain saturation voltage using the drain junction capacitance–voltage data of a metal–oxide–semiconductor field-effect transistor (MOSFET). When voltage is applied to the gate terminal, the drain and source are connected electrically via a surface inversion charge, and drain junction capacitance increases. When drain voltage increases, the pinch-off occurs at the drain end of the channel, and drain junction capacitance is rapidly reduced. Through this phenomenon, we can extract the drain saturation voltage directly from the drain junction capacitance–voltage curve without using complex mathematical formulas.

Physics-based compact model for ultra-scaled FinFETs

A physical and explicit compact model for lightly doped FinFETs is presented. This design-oriented model is valid for a large range of silicon Fin widths and lengths, using only a very few number of model parameters. The quantum mechanical effects (QMEs), which are very significant for thin Fins below 15 nm, are included in the model as a correction to the surface potential. A physics-based approach is also followed to model short-channel effects (roll-off), drain-induced barrier lowering (DIBL), subthreshold slope degradation, drain saturation voltage, velocity saturation, channel length modulation and carrier mobility degradation. The quasi-static model is then developed and accurately accounts for small-geometry effects as well. This compact model is accurate in all regions of operation, from weak to strong inversion and from linear to saturation regions. It has been implemented in the high-level language Verilog-A and exhibits an excellent numerical efficiency. Finally, comparisons of the model with 3D numerical simulations show a very good agreement making this model well-suited for advanced circuit simulations.

Insights Into the Design and Optimization of Tunnel-FET Devices and Circuits

Improving the on-current has been the focus of enhancing the performance of tunnel field-effect transistors (TFETs). In this paper, we show that the increase in I_ON is not sufficient to improve the circuit performance with TFETs. As TFETs show a drain-barrier voltage in their output characteristics below which the drain current drastically reduces, the rise/fall time significantly increases. This reduces the dynamic noise margin and limits the performance achievable from TFETs. We show that, in TFETs, the delay of the circuit is determined by the rise/fall time rather than by the propagation delay. The saturation voltage is much higher compared with that of complementary metal-oxide-semiconductor (CMOS) devices, leading to a lower gain and a lower static noise margin in digital circuits, as well as impeding the performance of latch/regenerative circuits. We present a design space comprising of I_ON, a drain saturation voltage, and a drain threshold voltage for minimizing the propagation delay of circuits using TFETs. Finally, for the same off-current and speed of operation, TFET devices tend to suffer from a higher gate capacitance compared with CMOS devices. If this behavior is not taken into account during the circuit design, these devices (although designed for low-power applications) can dissipate more power at the same speed of operation than CMOS counterparts.

Ambient field effects on the current-voltage characteristics of nanowire field effect transistors

We investigate the effects of ambient field from the gate and drain contacts on the current-voltage characteristics of a vertical nanowire field effect transistor having a lightly doped ungated length near the drain. Such a device is suitable for high voltage (tens of volts) applications. It is shown that the ambient field enhances the carrier concentration and divides the ungated region into gate-controlled and drain-controlled sections, controllable by the drain contact size and bias-voltages. These phenomena have a significant impact on the drain breakdown voltage, saturation voltage, saturation current and output resistance. The effects are established with the help of measured data and numerically calculated current-voltage curves and field lines.

Explicit Compact Model for Ultranarrow Body FinFETs

An explicit charge-based compact model for lightly doped FinFETs is proposed. This design-oriented model is valid and continuous in all operating regimes (subthreshold, linear, and saturation) for channel lengths ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">L</i> ) down to 25 nm, Fin widths ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">W</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Si</sub> ) down to 3 nm, and Fin heights ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">H</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Si</sub> ) down to 50 nm with a single set of parameters. It takes short-channel effects, subthreshold slope degradation, drain-induced barrier lowering, drain saturation voltage with velocity saturation, channel length modulation, and quantum mechanical effects into account.