A Novel ${{V}}_{\textsf {DSAT}}$ Extraction Method for Tunnel FETs and Its Implication on Analog Design

Abstract

This brief investigates for the first time, a method to extract the value of saturation drain voltage for a tunnel FET. The saturation in output characteristics of a TFET is found to take place when the difference in conduction band energy ( $\Delta {\textsf {E}}_{{\textsf {C}}}$ ) of channel ( ${{E}_{\text{CC}}}$ ) and drain ( ${{E}_{\text{CD}}}$ ) is a few ${{K}_{B}}{T}$ . As the drain voltage ( ${{V}_{\text{DS}}}$ ) increases, it is found that the device initially enters in a soft saturation state and subsequently into deep saturation. For any given value of gate voltage ( ${{V}_{\text{GS}}}$ ), the onset of soft and deep saturation happens for a constant difference in ${{V}_{\text{GS}}}$ and ${{V}_{\text{DS}}}$ . We propose a novel method to extract this voltage difference ${{V}_{\text{GD}}}$ , which is explained using a phenomenological approach. We have also validated our results with published experimental data. It is found that the output resistance ( ${{R}_{o}}$ ), transconductance ( ${{g}_{{m}}}$ ), and intrinsic gain ( ${{g}_{{m}}}\times {{R}_{{o}}}$ ) increase when the device enters in a soft saturation and attain a maximum value in deep saturation regime. Furthermore, a common source amplifier biased in soft saturation is also demonstrated to have a comparable voltage gain and bandwidth to the one biased in deep saturation.