Abstract
In this work, the mechanism and model of saturation drain voltage (Vds,sat) for Junctionless FinFET (JLF) are investigated. The Vds,sat of JLF is observed to increase linearly with gate voltage in all operation regions. A physics-based Vds,sat calculation model of JLF is built for fast and simple extraction of saturation drain voltage. The effects on Vds,sat of device parameters such as gate length, Fin height, Fin width and doping concentration, as well as device structure such as top gate and corner of the Fin, are discussed by simulation and model calculation. The results of model meet well with the simulation, and JLF has a low Vds,sat compared with other FinFETs. It shows that JLFs have potential prospect for lower power application in the future.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
