Abstract
Junctionless (JL) FinFET is one of the most promising alternatives to FinFET and planar MOSFET for future performance enhancements. The complexity of the JL FinFET manufacturing process has prompted difficulties in reliable device testing. Gate oxide short (GOS) is one of the most common faults that substantially influence circuit reliability, specifically in FinFET device structure. In this work, GOS defect model is presented for both n-channel and p-channel JL FinFET and JL FinFET-based inverter by introducing the defect as a pinhole designated by small cuboid cuts of different sizes for several coordination in the dielectric and filled with gate material. The electrical characteristics of 15nm n- and p-channel JL FinFET with fin height and width of 10nm, source/drain, channel and substrate doping concentration of 1.5×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">19</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">−3</sup> , and work function of 4.76eV and 4.52eV for n- and p-channel are successfully simulated by using Synopsys Sentaurus TCAD Tools where Vth, SS, and DIBL are 0.371V, 75.7mV/dec and 42.7mV for n-channel and 0.3298V, 79.1mV/dec and 48.9mV for p-channel JL FinFET respectively that is compared with post GOS defect injection. The high-to-low delay time (t <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">HL</inf> ) is 1.61ps and low-to-high delay time (t <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LH</inf> ) is 1.74ps for the defect-free inverter that is compared to the defected one where the t <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">HL</inf> is 16.1 % and t <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LH</inf> is 22.4 % smaller than defective inverter. The findings of this research potentially result in the formation of a realistic analytical GOS fault model for circuit-level modeling.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
