Effects of the correlation length of line edge roughness on the variability of 14-nm inversion-mode and junctionless FinFETs

Abstract

ABSTRACTIn this paper, we investigated the effects of the correlation length of line edge roughness (LER) on the variability of 14-nm inversion mode (IM) and junctionless (JL) FinFETs by technology-computer-aided-design simulation. We examined the effects of the correlation length of gate LER (GLER) and of fin LER (FLER) on the device variability separately. The simulation results show that, for the 14-nm IM FinFET, both the GLER-induced and FLER-induced device variations will decrease as the correlation length of LER increases. Therefore, increasing the correlation length of LER is also an effective way to reduce the LER-induced device variations besides decreasing the rms amplitude (σ) of LER. In addition, as far as LER is concerned, GLER is the major source for device variations when devices operate in the subthreshold region and FLER is the major source for device variations when devices are in the ON state. However, for the 14-nm JL FinFET with the same fin geometry as the IM FinFET, the FLER-induced device variations are larger than the GLER-induced device variations and will increase as the correlation length of FLER increases. Therefore, for the 14-nm JL FinFET, increasing the correlation length of LER will worsen the LER-induced device variations. Besides, LER will cause larger device variations on the JL FinFET than the IM FinFET.