Drain-induced Barrier Lowering Parameters Research Articles

TCAD analysis of conditions for DIBL parameter misestimation in cryogenic MOSFETs

Abstract The study aimed to investigate the transfer characteristics of metal-oxide-semiconductor field-effect transistors (MOSFETs) at cryogenic temperatures to elucidate the experimental conditions affecting the accurate estimation of the drain-induced barrier lowering (DIBL) parameter. Our device simulation revealed that MOSFETs featuring an underlap between the gate and source/drain edges experience a significant shift in threshold voltage (V t) in the low drain voltage (V d) region, which causes the misestimation of the DIBL parameter. This V t change is due to a notable increase in carrier concentration within the underlap region. To mitigate misestimation, confirming the dependence of the DIBL parameter on the linear region of V d serves as an effective method to ensure accurate estimation.

TCAD analysis of conditions for DIBL parameter misestimation in cryogenic MOSFETs

Abstract The study aimed to investigate the transfer characteristics of metal-oxide-semiconductor field-effect transistors (MOSFETs) at cryogenic temperatures to elucidate the experimental conditions affecting the accurate estimation of the drain-induced barrier lowering (DIBL) parameter. Our device simulation revealed that MOSFETs featuring an underlap between the gate and source/drain edges experience a significant shift in threshold voltage (V t) in the low drain voltage (V d) region, which causes the misestimation of the DIBL parameter. This V t change is due to a notable increase in carrier concentration within the underlap region. To mitigate misestimation, confirming the dependence of the DIBL parameter on the linear region of V d serves as an effective method to ensure accurate estimation.

Modeling of Ballistic Monolayer Black Phosphorus MOSFETs

In this paper, we present two accurate physics-based models of ballistic metal–oxide–semiconductor field-effect transistors (MOSFETs), both using less than ten parameters. These models—the capacitor model and the virtual source model—are based on the Landauer–Buttiker formalism. We show that the nonthermalization of charge carriers in the channels of ballistic MOSFETs leads to two critical effects that need to be considered in the modeling: the ballistic drain-induced barrier lowering (DIBL) effect and the floating source effect. The ballistic DIBL effect is responsible for a drain voltage dependence of the DIBL parameter; the floating source effect intensifies the injection of high-energy carriers from the source as the gate voltage increases. Specifically, the analysis is carried out on devices composed of monolayer black phosphorus, a 2-D semiconductor with unique electronic and mechanical properties, which make it a promising candidate for 2-D digital logic applications.

Investigation and Comparison of the DIBL Parameter and Thermal Effects of SOD Transistors and SOI Transistors and Improving Them with the Change of Their BOX Thicknesses

In this paper, thermal effects and Drain Induced barrier lowering (DIBL) of silicon-on-insulator (SOI) and silicon-on-diamond (SOD) transistors with 22 nm channel lengths using hydrodynamic simulations have been investigated. Thermal conductivity of diamond in contrast to thermal conductivity of silicon dioxide is significantly higher. Hence, the heat transfers faster in silicon-on-diamond transistors. Lattice temperature of SODs is lower than that of similar SOIs. By using SODs in Integrated circuits with the first transistor turning on and active, neighboring transistors will have the same level of heat as the active transistor. As a result, the DIBL factor will be increased; this is an undesired phenomenon in CMOS applications. To resolve this issue, we propose a new method which is the thickness reduction of buried diamond layers inside of transistors. Due to this change, DIBL of active transistor will be improved, the exceeding lattice heat of side transistors will be evacuated through the devices and their temperatures will be deduced in large scale.

Enhanced Radiation Sensitivity in Short-Channel Partially Depleted Silicon-on-Insulator n-Type Metal-Oxide-Semiconductor Field Effect Transistors

The total ionizing dose effects of partially depleted silicon-on-insulator (SOI) transistors in a 0.13 μm technology are studied by 60Co γ-ray irradiation. Radiation enhanced drain-induced barrier lowering (DIBL) under different bias conditions is related to the parasitic bipolar in the SOI transistor and oxide trapped charge in the buried oxide, and it is experimentally observed for short channel transistors. The enhanced DIBL effect manifests as the DIBL parameter increases with total dose. Body doping concentration is a key factor affecting the total ionizing dose effect of the transistor. The low body doping transistor exhibits not only significant front gate threshold voltage shift as a result of the coupling effect, but also great off-state leakage at high drain voltage due to the enhanced DIBL effect.

Total Ionizing Dose Enhanced DIBL Effect for Deep Submicron NMOSFET

Radiation enhanced drain induced barrier lowering (DIBL) effect under different bias conditions was experimentally observed and verified by 3D simulation for deep submicron MOSFETs with shallow trench isolation (STI) oxides. The off-state leakage current increased significantly after total ionizing dose (TID) above 200 krad(Si) for PASS ,OFF and ON bias condition. The irradiated devices exhibited enhanced DIBL effect, that is the off-state leakage current increases with drain voltage and DIBL parameter increases with TID. The oxide trapped charge in the STI sidewall enhances the DIBL by decreasing the drain to gate coupling, enhancing the electric field near the STI corner, and increasing the surface potential of lowly doped substrate along STI sidewall. A simple dipole theory describing the enhanced DIBL phenomenon is introduced. The phenomenon is a result of the electrostatic effect, which concentrates drain field on channel into the source along shallow trench isolation oxide. Effective non-uniform charge distribution is applied in the 3D simulation for the radiation enhanced DIBL effect. Good agreement between experiment and simulation results is demonstrated.

An analytical study of undoped symmetric double gate MOSFET (SDG)

AbstractIn the present paper, compact analytical models for the threshold voltage, threshold voltage roll‐off and subthreshold swing of undoped symmetrical double‐gate MOSFET have been developed based on analytical solution of two‐dimensional Poisson's equation for potential distribution. The developed models include drain‐induced barrier lowering (DIBL) through the Vds‐dependent parameter. The calculated threshold voltage value, obtained from the proposed model, shows a good agreement with the experimental and published results. The simulation results for potential show that the conduction is highly confined to the surfaces. The threshold voltage sensitivity to the thickness is found to be approximately 0.2%. Model prediction indicates that subthreshold slope is not linearly related to DIBL parameter for thick silicon film. The proposed analytical models not only provide useful insight into behavior of symmetrical DG MOSFETs but also serve as the basis for compact modeling. Copyright © 2010 John Wiley & Sons, Ltd.

An accurate two-dimensional CAD-oriented model of retrograde doped MOSFETs for improved short channel performance

An analytical CAD-oriented model for short channel threshold voltage of retrograde doped MOSFETs is developed. The model is extended to evaluate the drain induced barrier lowering parameter ( R) and gradient of threshold voltage. The dependence of short channel threshold voltage and R on thickness of lightly doped layer ( d) has also been analyzed in detail. It is shown that a retrograde doping profile reduces short channel effects to a considerable extent. A technique is developed to optimize the device parameters for minimizing short channel effects. The results so obtained are in close proximity with published data.

Temperature dependence of drain-induced barrier lowering in deep submicrometre MOSFETs

A new method for extracting the drain-induced barrier lowering (DIBL) parameter in an MOS transistor is proposed. This method is used to study the influence of temperature on the DIBL effect. It is found that the DIBL parameter is almost independent of temperature between 50 and 300K. This method makes it also possible to recalculate the intrinsic output characteristics that the device would have in the absence of DIBL, and, in turn, to evaluate the intrinsic device saturation parameters.

Drain-induced barrier-lowering analysis in VSLI MOSFET devices using two-dimensional numerical simulations

In recent publications the drain-induced barrier-lowering (DIBL) effect has been included in the determination of the drain current of short-channel MOSFET's by way of analytical expressions. The validity of these published expressions has not been verified so far for small-geometry devices of different parameters. Further, the relationship between the threshold voltage shift and the barrier lowering due to the DIBL effect has not been clarified in the literature. In our present paper we carried a detailed study of the drain-induced barrier lowering in ion-implanted 1-µm VLSI MOSFET devices, leading to a better understanding and clarification of the fundamental mechanisms involved in the DIBL variation and its effect on the threshold voltage and subthreshold current. Further, we found that the calculated DIBL parameters of the analytical model reported in the literature do not agree with the numerically computed values. Hence we determined a set of new geometry parameters η and B/A for the DIBL threshold relationship that can be used with the analytical model. Our work stresses the necessity of the use of two-dimensional numerical simulations when accurate evaluation of the DIBL effect in short-channel MOSFET's is required. Also, our results should be useful for calibrating existing analytical MOSFET models. In addition, our data and method could be used as a design tool for performance optimization of micrometer and submicrometer devices.