Drain Extension Research Articles

Technological developments toward deep sub-micronp-MOS transistors

This article presents a position statement involving research toward the technological feasibility of producing p-MOS transistors with actual channel lengths approaching dimensions less than 100 nm. This work is part of a complementary programme where the theoretical possibility of scaling to such dimensions are also being studied. However we address here what we consider to be the major technological issues, namely the gate dielectric, source drain extensions and the composition of the gate material

Fabrication of compact 100 nm-scale silicon metal–oxide–semiconductor field effect transistors

The fabrication of exploratory silicon metal–oxide–semiconductor field effect transistors in which all device levels meet 100 nm groundrules is reported. The device design incorporates several novel features which allow for an ultracompact structure. These features include shallow trench isolation, over-the-gate contacts, fully overlapped source, drain and gate contacts and shallow source and drain extensions. This article offers a detailed description of the fabrication process, with an emphasis on high resolution, high accuracy electron beam nanolithography and new reactive ion etching processes. Complete process integration is described which culminates in the successful fabrication of functional compact devices.

PMOSFET hot-carrier damage: oxide charge and interface states

The hot-carrier degradation mechanism in PMOSFETs (p-channel metal-oxide-semiconductor field-effect transistors) is studied for three transistor types over ten orders of magnitude in time. The authors observe oxide charge and interface states separately by charge pumping. Degradation for various gate lengths at many gate and drain voltages is measured and interpreted consistently. Negative oxide charge and interface states are generated by electrons near the drain. This charge attracts an inversion layer that extends the drain and reduces the effective transistor length logarithmically in time, simultaneously preventing degradation of the transistor operation by the generated interface states. However, holes may generate interface states outside the drain extension, decreasing the transconductance with a power of time.

Structural properties of electron beam evaporated zinc sulphide thin films : I. Esquivias, M. Recio, T. Rodriguez and J. Sanz-Maudes. Vacuum39(7/8), 723 (1989)

The impact of the spacer length at the source (Ls) and drain (Ld) on the performance of symmetrical lightly-doped double-gate (DG) MOSFET with gate length L = 20 nm is analyzed, with the type and doping concentration of the spacers kept the same as in the channel material. Using the transport parameters extracted from experimental data of a double-gate FinFET, simulations were performed for optimization of the underlapped gate-source/drain structure. The simulation results show that the subthreshold leakage current is significantly suppressed without sacrificing the on-state current for devices designed with asymmetrical source/drain extension regions, satisfying the relations Ls = L/2 and Ld = L. In independent drive configuration, the top-gate response can be altered by application of a control voltage on the bottom-gate. In devices with asymmetrical source/drain extension regions, simulations demonstrate that the threshold voltage controllability is improved when the drain extension region length is increased.

HIGH VOLTAGE SWITCHING P-CHANNEL STRUCTURE FOR CMOS ARCHITECTURES

An analysis of a P-ch High Voltage structure fully compatible with all CMOS architectures is presented. It points out the critical role played by drain extension layer on electrical derier performance, and by the field thick oxide periphery on the device reliability. These results are useful in designing HV process compatible devices in advanced CMOS technology.

Development of a new self-aligning contact technology

A self-aligning contact process (SACMOS) for MOS/VLSI technology is described. A new technique involving submerged implant into the source and drain is employed. This enables the enhanced oxidation of the previously heavily doped polysilicon gate compared to the more lightly doped source and drain. The implant also provides the source and drain extensions. During oxidation, silicon nitride pads protect all contacts. A noncritical masking and etching stage is used to yield contacts. The process uses two extra masking stages to produce self-aligned contacts to the source, drain, and gate of MOS transistors, yielding a significant reduction in the area required for contact regions and hence a greater packing density. A process verification chip illustrated that discrete transistors designed using the new process exhibited similar properties to conventionally designed devices. Also a 21-stage ring oscillator designed with a minimum dimension of 6 µm occupied 15 percent less space than a conventional device and operated at the same speed under similar bias conditions. Finally it is estimated that a ROM designed using the new process occupies 25 percent less space.

A new CMOS IC structure and its characterization

In this paper a new N-channel MOS transistor structure providing the improvement of electrical characteristics with respect to the conventional structure and simplified fabrication compared to generally accepted drain extension structure is presented. Description and optimisation of technologycal procedure for fabrication of the new N-channel MOS transistor structure are given. Also, static and dynamic characteristics of the N-channel MOS transistor realized by new procedure are investigated and compared to the corresponding characteristics of N-channel MOS transistors realized by conventional and drain extension procedures. Finally, reliability of the CMOS ICs realized by new procedure is investigated using both static and dynamic life tests.

A high-performance CMOS/SOS device with a gradually doped source—Drain extension structure

A gradually doped source-drain extension (GDDE) CMOS/SOS structure with n+ poly gate has been used to fabricate a high-performance CMOS/SOS inverter ring oscillator and 1%8 static binary counter. The 0.8-µm gate ring oscillator shows 80-ps stage delay at V_{DD} = 5 V, and it achieves 0.1 pJ of speed-power product with 95-ps stage delay. The plasma-etched epi island minimizes the edge leakage current, as shown in subthreshold characteristics.

Self-registered gradually doped source drain extension short channel CMOS/SOS devices

The oxide sidewall-spacer technology was utilized to fabricate CMOS/SOS devices with the self-registered gradually doped source drain extension structure. No additional photo masking or ion implantation steps are required than in the case of a conventional polysilicon gate CMOS/SOS process. The devices revealed significant improvements in the breakdown voltage, leakage current and the short channel effect.

Reliable software through requirements definition using data abstractions : William R. Bezanson. Microelectron. Reliab.17, 85 (1978)

Novel single-sided non-overlapped implantation (SNOI) nMOSFETs are characterized for their capability of multiple programmable memory functions. These devices can be operated as mask ROMs, EEPROMs or anti-fuses by using a pure logic processing. To function as mask ROMs, they can be mask-coded with the source drain extension (SDE) implantation. They can also be used as EEPROM devices by trapping charges in the side-wall nitride spacers. Furthermore, SNOI devices can be used as antifuses by introducing the punch-through stress at the drain side. The SNOI devices were successfully demonstrated for antifuse operations with an extremely high program/initial readout current ratio exceeding 109 and a program speed as high as 1 μs. These novel SNOI devices not only provide non-volatile memory solutions in standard CMOS processing but also give a flexible choice among mask ROM, antifuse and EEPROM functions.