Drain Extension Region Research Articles

Study on the regulation factors and mechanism of self-heating effects in non-rectangular 14 nm bulk FinFET*

Abstract This work investigates the innovative design of a 14 nm bulk 3D non-rectangular structure fin field-effect transistor (FinFET). By incorporating a cylindrical trapezoidal structure into the upper portion of the FinFET, it transcend the limitations posed by the self-heating (SH) effect observed in traditional rectangular fins.Through the density gradient model and thermal conduction model, the changes in the electron carrier temperature and lattice temperature of the channel are studied, and the relationship between electrical properties and thermal resistance was further analyzed, revealing the effect of SH on the threshold voltage and switching speed of the device. In addition, the SH effect of the doping of source and drain extension regions was also explored, and the effects of electron mobility changes at different ambient temperatures were also studied to clarify their impact on the electrical properties. Ultimately, this work offers novel insights into the design, optimization, and reliability studies of device structures affected by SH effects.

Optimization of negative capacitance junctionless gate-all-around field-effect transistor using asymmetric non-local lateral Gaussian doping

Technology advancements directed towards Internet-of-Things (IoT) and wearable computing electronics applications are booming in low-power devices, which requires downscaling of power supply voltage without sacrificing the performance of the device. A negative capacitance junctionless gate-all-around field-effect transistor (NC-JL-GAAFET) is investigated using technology computer-aided design (TCAD) simulations to further suppress the short-channel effects and reduce power consumption. Lateral Gaussian doping (LGD), proposed for the NC-JL-GAAFET, is considered its main doping mode. An asymmetric structure with varying lengths of source/drain extension regions is introduced into non-local LGD NC-JL-GAAFET. The results reveal that the proposed device with a larger length ratio for drain extension region has a higher switching current ratio and lower subthreshold swing. Furthermore, the TCAD simulations validate that the electrical characteristics can be easily optimized by adjusting the ferroelectric (FE) layer thickness on the gate stack. Therefore, an asymmetric non-local LGD NC-JL-GAAFET provides a potential scaling solution for the next-generation low-power devices.

Performance Analysis of Tunnel FET Based Ring Oscillator Using Sentaurus TCAD

A detailed Sentaurus TCAD simulation based study for Silicon Double Gate Tunnel Field Effect Transistor (Si-DG TFET) based Ring Oscillator (RO) is presented in this work. Two different ring oscillator topologies (simple RO and Negative Skewed Delay RO )are presented with two different structures for TFET device. The two structures are different in the source-drain extension regions widths. The extension region width variation effects are studied and presented for inverter and ring oscillator. A TFET based inverter is presented to show the changes in behavior due to variations in the drain extension region widths, which is later used for RO designs. The drain extension region width changes the drain extension region resistances which in turn is responsible for change in the corresponding device properties. RO simulation are used for calculating the delay. To further explore digital and analog applications transfer characteristics and noise margins of inverter are explored with power supplies variations. Better reliability for oscillation frequency is obtained using Negative Skewed Delay ring oscillator (NSD RO) topology. NSD RO is resulting in lesser jitter, more reliable frequency as compared to single-ended ring oscillator topology. By tuning the supply voltage of the device the ring oscillator frequency can be used for RF applications, thus it works like a voltage controlled oscillator (VCO).

Impact of Non-Uniform Doping on the Reliability of Double Gate JunctionLess Transistor: A Numerical Investigation

This paper systematically studies the reliability of non-uniformly doped Double Gate Junctionless transistor using ATLAS TCAD simulation. The reliability analysis is mainly based on the understanding of Band-To-Band-Tunneling (BTBT) current, lattice temperature, drain conductance and gate leakage current. Presented results show that higher source/drain work-function is beneficial in reducing tunneling current (1 × 10−9 A to 4 × 10−11 A @ V gs = −1 V) but eventually it will also degrade electrostatic current significantly (∼3 order). Source/Drain length has also been varied during optimization and it has been observed that, shorter source drain extension region degrades the device reliability (i.e. higher magnitude of tunneling current (7 × 10−9 A @ V gs = −1 V for L S = L D = 5 nm)). Different doping profile considered for performance assessment are: uniform, step (i.e. low–low–high and high–high–low etc.) and different configurations of gaussian doping profile. Minimum variation in tunneling current with negative gate bias, i.e. ∼ 1 order has been seen from the device having uniform doping 1019 cm−3 but at the cost of significantly high off-state current (2 × 10−9 A @ V gs = 0 V) and tunneling current (2 × 10−8 A @ V gs = −1 V). Thus, instead of using uniform doping, step type profile (i.e. Case A) is the better choice which results in lower tunneling current (1 × 10−9 A @ V gs = −1 V), moderate lattice temperature (326) and better I on/I off ratio (243 × 108). Device lattice temperature has also been controlled by using step A doping profile even at the higher operating temperatures due to lower Self Heating Effect.

Parasitic NPN and PNP Latch-Up Within a Single DMOS for High Voltage Reliability

This article discusses the robustness of field-plate-assisted reduced surface field effect (RESURF) DMOS designs to time-dependent latch-up within a single dielectrically isolated device. This work individually characterizes the dopant defined parasitic bipolar parallel to all MOS and uniquely describes the existence of another parasitic bipolar of opposite polarity through the generation of a backgate current as a result of weak impact ionization. These two NPN and PNP bipolar devices in a single DMOS device complete the latch-up mechanism once the product of their gains is greater than one. The characterized time-dependent nature of the increasing backgate current is accounted for by oxide charge trapping in the extended drain region, where measurements of this mechanism over a broad range of application and manufacturing variables enable a mathematical model for the time to failure to be described. Finally, the advantage of analyzing DMOS latch-up robustness in the context of individual parasitic NPN and PNP bipolar devices is shown by its ability to isolate out the separate variables feeding into each bipolar to implement robust solutions.

A New Aspect of Saturation Phenomenon in FinFETs and Its Implication on Analog Circuits

This paper presents a physics-based semiempirical model of drain saturation voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS,SAT</sub> ) of a FinFET device suitable for analog circuit design. The previous belief of similarity of the saturation phenomenon in the FinFET and planar MOSFET devices is investigated for the first time and is shown to be inconsistent in the FinFET device. When the value of V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> is increased to V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS,SAT</sub> , then at a critical point, the product of electron density (n) and electron velocity (v <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d</sub> ) starts decreasing at the silicon-dielectric interface while it increases at the mid of the fin. This critical point lies within the drain extension (DE) region near to channel-DE junction. It is also observed that V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS,SAT</sub> increases linearly with V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS,</sub> (≥0.6 V). Based on this, a semiempirical V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS,SAT</sub> model is proposed, which is simple enough to be usable in analog circuit design. Moreover, compared to planar devices, a strikingly different trend of the output resistance (r <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">o</sub> ) in FinFET is observed. We explained this behavior for the first time using our understanding of FinFET saturation phenomenon. By employing our semiempirical model of V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS,SAT</sub> and the trend of r <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">o</sub> with V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> , we estimated the bias voltages of the FinFET amplifier to improve the gain by about 3× while not increasing the power dissipation. Since the gains of cascode and telescopic cascode amplifiers are strongly dependent on r <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">o</sub> , these FinFET amplifiers can be designed to have much smaller overdrive voltages compared to its planar counterparts.

Ultra-Shallow Junction Formation by Monolayer Doping Process in Single Crystalline Si and Ge for Future CMOS Devices

We focused on the damage-free monolayer doping (MLD) method starting from a chemical reaction of molecules on Si and Ge surfaces and applied it to 3D MOSFET device fabrication. MLD methods were verified by different material analysis, such as XPS and Raman spectroscopy. For a Si-based FinFET structure, compared to the device with ion implantation, the short channel effect of source and drain (SD) extension regions formed by MLD are improved. The shallower SD extension regions formed by low-temperature microwave annealing (MWA) are expected to the device showing better electrical properties than deeper ones formed by RTA. In addition, formation of the n- and p-type doping in Ge by MLD was also investigated. Even after annealing at 800°C for 300 sec by RTA, the p-type doping still exhibits a low surface doping concentration due to the low diffusion coefficient of B in Ge and surface diffusion limitations at the MLD/Ge interface. By using a combination of RTA and CO2 laser spike annealing (LSA), MLD n-type doping in Ge are formed with junction depths of ≈15 nm, and peak concentration of ≈ 6 × 1020 atoms/cm3. The dopant activation for the MLD-doped channels of Ge junctionless FinFETs (JLFinFETs) is improved after the additional CO2 LSA.

A Reliable Nano Device with Appropriate Performance in High Temperatures

There are many problems during designing MOSFETs in nano scale regime. Some problems contain high gate current, high off current and high electron temperature. These problems are created when the peak of electric field is high which causes reducing the device reliability. So, reducing the peak of electric field can be an objective during designing a device. In this paper, a new structure for improvement of the partial SOI MOSFET parameters is presented. So, oxide layers are considered in the channel and in the extended drain region to reduce the peak of electric field. This reduction results in achieving reduced off current, gate current and electron temperature. The simulation with ATLAS simulator shows that the new structure has improved hot carrier effect and its reliability is more than conventional one.

An Accumulation Mode RF Laterally Double Diffused MOSFET With Improved Performance

In this letter, an improved radio frequency (RF) laterally double diffused metal–oxide–semiconductor (LDMOS) transistor with the application of accumulation mode stripe (AMS) is proposed and fabricated in a 0.35- $\mu \text{m}$ CMOS process without extra process steps or masks. AMS accumulates electrons at the surface of the drift region, which result in an improvement in the saturated drain current. Moreover, AMS modulates the electric field distribution across the drain extension region by inducing an electric field peak at its edge. Power performances at 3.1 GHz for the AMS-LDMOS show a 0.75-W/mm continuous-wave output power density with 21-dB linear gain and over 52% drain efficiency at a supply voltage of 32 V. In comparison with conventional RF LDMOS with source field plate, the proposed device exhibits 1–1.5 dB higher linear gain along with improved linearity.

Atypical Voltage Transitions in FinFET Multistage Circuits: Origin and Significance

For optimizing FinFET circuit-level parameters (such as number of fins) with performance predictability, it is necessary to understand the nature of voltage transitions at the nodes of a multistage logic circuit. Since the device’s extension region parasitics are strong, these transitions need to be studied while considering them. We find using Technology Computer aided design simulations that the transitions at the input/output nodes of FinFET inverter chain stages are unconventional in nature for an important range of fan-out loads and input transition time values. The transition has three parts. First, a monotonous increase/decrease, followed by a duration of slowly varying voltage (which we call drag), and again followed by a monotonous increase/decrease. The duration of this drag is a strong function of a circuit’s transistor sizing (number of fins). We explain this phenomenon to be due to the strong gate-controlled modulation of carrier densities in the low-doped part of the drain extension region. We demonstrate that this phenomenon has serious implications on circuit delay and power consumption.

Determination of active oxide trap density and 1/f noise mechanism in RESURF LDMOS transistors

The physical origin of majority charge carrier fluctuations in the SiO2 interface of Si at accumulation has been investigated and analyzed for differently processed and voltage-rated reduced surface field (RESURF), lateral-double-diffused MOS (LDMOS) transistors. Surface carrier mobility fluctuation due to remote Coulomb scattering by the trapped charge in the gate oxide is identified as the dominant physical mechanism for LDMOS 1/f noise irrespective of process technologies. A significant contribution to the measured noise has been noted from the surface majority carrier mobility fluctuation due to trapped charge at the accumulation region of the extended drain region, dominant over other sources including the surface minority charge carrier fluctuations in the channel. Active oxide trap density was characterized spatially and for the first time up to ∼0.4eV above the conduction band-edge of Si. The interface trap density in the unstressed devices (∼8×106cm−2) increased more than an order of magnitude (∼1×108cm−2) after the devices were stressed for 10,000sec at their individual worst drain current and on-resistance degradation conditions. The extracted Si/SiO2 interface trap density above the silicon conduction band edge was found to be several orders of magnitude lower than that reported for silicon mid-gap energies, even after stressing. Since the traps near the quasi-Fermi level for electrons are active in trapping–detrapping, and the Fermi level is energetically positioned above the conduction band edge of Si in the investigated devices as compared to the previously reported observations, the lower trap density obtained here is an indication for reversal of the well-known exponential trap energy distribution beyond the conduction band-edge of Si. These findings shift the focus from the channel to the gate overlap section of the extended drain and the quality of the Si/SiO2 interface in that region.

Random Dopant Fluctuation Induced Variability in Undoped Channel Si Gate all Around Nanowire n-MOSFET

In this brief, the random dopant fluctuation (RDF)-induced threshold voltage (VT) variability, ON current (ION) variability, and VT mismatch in undoped channel Si gate-all-around (GAA) n-nanowire MOSFETs (n-NWFETs) are studied using coupled 3-D statistical device simulations considering quantum corrected room temperature drift-diffusion transport. The RDFs are introduced in the Si NWFET tetrahedral device grid by a 3-D atomistic MonteCarlo technique. The RDF due to discrete random dopants located in the source (S)/drain (D) extension and channel regions of Si GAA n-NWFET are found to impact the device characteristic variability. The numerical VT mismatch analysis and comparison with the Si n-NWFET total AVT measurement data from the literature reveal that RDF still plays a significant source for device random fluctuations in undoped channel Si GAA n-NWFETs. The numerical VT mismatch study indicates the fact that complete suppression of RDF induced device random variability in undoped channel fully depleted MOS devices is still going to be a challenge, as long as doped S/D regions are employed.

Vertical gate-all-around junctionless nanowire transistors with asymmetric diameters and underlap lengths

Vertical gate-all-around (GAA) junctionless nanowire transistors (JNTs) with different diameters and underlap lengths are investigated using three-dimensional device simulations. The source-side diameter determines the on-current and drain-induced barrier lowering characteristics, whereas the drain-side diameter controls the band-to-band tunneling current during off-state conditions. The JNTs with short drain-side underlap lengths decrease the source/drain series resistance but increase the off-current values, especially due to large band-gap narrowing effects at the drain extension region. Proper device design of vertical GAA JNTs considering the device structure and underlap is needed to improve both on/off and short channel characteristics.

Ultra Low Power Junctionless MOSFETs for Subthreshold Logic Applications

In this paper, we report the potential of junctionless (JL) MOS transistors for ultra low power (ULP) subthreshold logic applications. It is demonstrated that double gate (DG) JL devices, which do not require source or drain extension region engineering, can perform significantly better than conventional inversion mode devices, and comparable with underlap DG MOSFETs for ULP applications. Sensitivity analysis shows that among all device parameters, JL devices exhibit least sensitivity to gate length in comparison with inversion mode and underlap MOSFETs. Results highlight the advantages and challenges of JL transistors for next-generation ULP CMOS logic devices.

A Physics-Based Analytical $\hbox{1}/f$ Noise Model for RESURF LDMOS Transistors

A physics-based model has been implemented to describe the low-frequency noise behavior in differently processed reduced-surface-field lateral double-diffused MOS devices. The developed model is based upon the correlated carrier number and the mobility fluctuation theory known as the unified model but has been modified to account for the fluctuations in the extended drain and the channel. Unlike the unified 1/f noise model, nonuniform trap distribution has been taken into account with respect to position in the gate oxide and band-gap energy. The effect of stress on dc and noise characteristics has been investigated. Individual resistance and noise components in the channel and in the extended drain regions under the gate and field oxides are evaluated as a function of stress duration. The model is experimentally verified to identify the physical mechanisms for degradation due to stressing.

Current Degradation in GaN HEMTs: Is Self-Heating Responsible

Electrical reliability of GaN HEMT system in both the on state and the off state regime is still a fundamental problem to be solved. To get an insight for the occurrence of the current collapse phenomena in GaN HEMTs, an electro-thermal particle based device simulator consisting of a Monte Carlo-Poisson solver, self consistently coupled with an energy balance solver for both acoustic and optical phonons, was developed. We observe that the incorporation of self-heating effects leads to an increase in the vertical electric field in the gate to drain extension region which can lead to large charge trapping on the surface and also the possibility of forming cracks or pits.

Effect of Stress-Induced Degradation in LDMOS $\hbox{1}/f$ Noise Characteristics

Low-frequency noise in double reduced-surface-field lateral-double-diffused-MOS devices has been measured, and the effect of dc stressing is analyzed. The noise components contributing from the extended drain regions under the gate and field oxides were differentiated from the channel noise by a series of experimental and analytical techniques. The effect of voltage stressing on each noise component was investigated. Trapped-charge carrier fluctuations due to Si/SiO2 interface traps in the overlap region in the extended drain as well as in the channel were found to be the dominant source of noise. The bulk resistance fluctuations in the extended drain region under the field oxide were found to be insignificant. High-voltage stressing caused an increase in the interface traps, thus increasing both the extended drain overlap resistance and the noise.

Electrothermal theory of photomodulated optical reflectance on active doping profiles in silicon

The electrical characterization of the source and drain extension regions of complementary metal oxide semiconductor (CMOS) transistors is highlighted in the international technology roadmap for semiconductors (ITRS) as a major challenge for future technology nodes. In practice, there is a clear need for techniques which are simultaneously accurate, nondestructive, fast, local, and highly reproducible. The photomodulated optical reflectance (PMOR) technique has shown to be a very promising candidate to solve this need. However, even though this technique has been widely studied on homogeneous bulk material and on as-implanted (i.e., unannealed) doping profiles, the extension toward active doping profiles requires a detailed investigation (due to the presence of a built-in electric field). In this paper, after performing an in-depth investigation of the optical and transport models involved in a PMOR experiment, we derive an analytical theory to explain the PMOR signal behavior observed on active doping profiles. In the optical model, we show that only the electrorefractive Drude and thermorefractive effects are to be considered for red and near-infrared wavelengths on Si. In the transport model, we begin the discussion with the study of homogeneous Si substrates. We show that, due to the high carrier injection induced by the lasers, the only important effects are, for the free carriers, the Auger recombinations, the (ambipolar) diffusion and the bandgap narrowing-induced quasidrift; the thermoelectric effects being negligible. Based on the results on homogeneous substrates and on the assumption that the quasi-Fermi levels are flat through the space-charge region, we derive an analytical formula for PMOR signals on active doping profiles. We discuss this formula based on experimental PMOR data measured on active doping profiles with a simple boxlike shape. This formula proves to be in good qualitative agreement with the experimental data both when the power of the pump laser is varied (power curves) and when the distance between the lasers is changed (offset curves). We also show that, for the formula to be quantitative, a very good knowledge of the bandgap profile throughout the sample would be required.

Source/drain optimization of underlapped lightly doped nanoscale double-gate MOSFETs

The impact of the spacer length at the source ( L s) and drain ( L d) on the performance of symmetrical lightly-doped double-gate (DG) MOSFET with gate length L = 20 nm is analyzed, with the type and doping concentration of the spacers kept the same as in the channel material. Using the transport parameters extracted from experimental data of a double-gate FinFET, simulations were performed for optimization of the underlapped gate-source/drain structure. The simulation results show that the subthreshold leakage current is significantly suppressed without sacrificing the on-state current for devices designed with asymmetrical source/drain extension regions, satisfying the relations L s = L/2 and L d = L. In independent drive configuration, the top-gate response can be altered by application of a control voltage on the bottom-gate. In devices with asymmetrical source/drain extension regions, simulations demonstrate that the threshold voltage controllability is improved when the drain extension region length is increased.

Nondestructive extraction of junction depths of active doping profiles from photomodulated optical reflectance offset curves

The ITRS Roadmap highlights the electrical characterization of the source and drain extension regions as a key challenge for future complimentary-metal-oxide-semiconductor technology. Presently, an accurate determination of the depth of ultrashallow junctions can routinely only be performed by time-consuming and destructive techniques such as secondary ion mass spectrometry (SIMS). In this work, the authors propose to use the fast and nondestructive photomodulated optical reflectance (PMOR) technique , as implemented in the Therma-Probe® (TP) dopant metrology system, for these purposes. PMOR is a pump-probe technique based on the measurement of the pump-induced modulated change in probe reflectance, i.e., the so-called (photo) modulated reflectance. In this article, the authors demonstrate that the absolute junction depths of boxlike active dopant structures can be extracted in a very simple and straightforward way from the TP offset curves, which represent the behavior of the modulated reflectance as a function of the pump-probe beam spacing. Although the procedure is based on the insights into the physical behavior of the offset curves, no modeling is involved in the actual extraction process itself. The extracted junction depths are in good correlation with the corresponding junction depths as measured by means of SIMS. The technique has a subnanometer depth sensitivity for depths ranging from 10to35nm with the present Therma-Probe® 630XP system. The extension of the proposed procedure to the general ultrashallow profiles is also explored and discussed.