Drain-extended MOS Transistors Research Articles

A Two-Module Linear Regulator with 3.9–10 V Input, 2.5 V Output, and 500 mA Load

A linear regulator with an input range of 3.9–10 V, 2.5 V output, and a maximal 500 mA load for use with battery systems was developed and presented here. The linear regulator featured two modules of a preregulator and a linear regulator core circuit, offering minimized power dissipation and high-level stability. The preregulator delivered an internal power voltage of 3 V and supplied internal circuits including the second module (the linear regulator core). The preregulator fitted with an active, low-pass filter provided a low-noise reference voltage to the linear regulator core circuit. To ensure operational stability for the linear regulator, error amplifiers incorporating the Miller compensation technique and featuring a large slewing rate were employed in the two modules. The circuit was successfully implemented in a 0.25 µm, 5 V complementary metal-oxide semiconductor (CMOS) process featuring 20 V drain-extended MOS (DMOS)/bipolar high-voltage devices. The total silicon area, including all pads, was approximately 1.67 mm2. To reduce chip area, bipolar rather than DMOS transistors served as the power transistors. Measured results demonstrated that the designed linear regulator was able to operate at an input voltage ranging from 3.9 to 10 V and offer a maximum 500 mA load current with fixed 2.5 V output voltage.

RESURF Model and Electrical Characteristics of Finger-Type STI Drain Extended MOS Transistors

Finger-type shallow trench isolation (finger STI) drain extended MOS transistors are fabricated and its electrical characteristics is studied. Polyplate on a finger STI served as a reduced surface field is adopted to enhance breakdown voltage (BV) by reducing the effective doping concentration of the drain extension (DE) finger. The conformal mapping method, which relates the reduction of the doping concentration to the width ( $z_{o}$ ) of the DE finger, the gap ( $z_{d}$ ) between the polyplate and the DE finger, and the STI depth $y_{s}$ , is used to estimate the reduction of the doping concentration theoretically. Based on this reduced doping concentration, a BV model is derived. The predictions of this model agree very well with the experimental data.

Part I: High-Voltage MOS Device Design for Improved Static and RF Performance

In this paper, for the first time, the key design parameters of a shallow trench isolation-based drain-extended MOS transistor are discussed for RF power applications in advanced CMOS technologies. The tradeoff between various dc and RF figures of merit (FoMs) is carefully studied using well-calibrated TCAD simulations. This detailed physical insight is used to optimize the dc and RF behavior, and our work also provides a design window for the improvement of dc as well as RF FoMs, without affecting the breakdown voltage. An improvement of 50% in $R_{\mathrm{{\scriptscriptstyle ON}}}$ and 45% in RF gain is achieved at 1 GHz. Large-signal time-domain analysis is done to explore the output power capability of the device.

Device–Circuit Co-design for Beyond 1 GHz 5 V Level Shifter Using DeMOS Transistors

This paper presents a device-circuit co-design approach to achieve a low swing, high speed 1.2-5 V level shifter (LS) using drain extended MOS (DeMOS) transistors for system on chip applications in advance CMOS technologies. Limiting factors of the high-voltage devices during transients are identified and accordingly it is shown that the maximum operating frequency of traditional LS can be increased by at least a factor of two. It is demonstrated that optimization of key device parameters of the DeMOS transistor enhances the maximum clock frequency to more than 1 GHz while preserving the device breakdown voltage and duty cycle of the level shifted signal.

Gate-Oxide Breakage Assisted by HCI in Advanced STI DeMOS Transistors

This letter provides, for the first time, experimental evidence supporting that hot-carrier injection not only degrades electrical performance in drain-extended MOS transistors with shallow trench isolation (STI DeMOS) but also induces a severe gate-oxide (Gox) degradation and wear-out of the oxide. During the Gox degradation at high-stress conditions, a steep increase of interface traps (Nit) and oxide traps (Not) is detected in the accumulation region by using charge pumping. A subsequent fast degradation of the device electrical characteristics is observed.

Drain-extended MOS transistors capable for operation at 10 V and at radio frequencies

This work reports on the integration of n-type lateral-drain-extended MOS transistors (LDMOS) in a 0.13μm SiGe BiCMOS technology. The transistors are realized with no additional process steps using the core dual-gate-oxide CMOS flow only. LDMOS drift regions are formed by compensating lightly-doped drain (LDD) implantations of NMOS and PMOS transistors of the baseline process. Stable operation with less than 10% parameter variations in 10 years is achieved up to operating voltages VDD,max of 10V for devices with breakdown voltages BVDSS=30V and on-resistances RON=7.3Ωmm. Devices for different operating voltages VDD,max are realized by layout variations. Devices with VDD,max=6V demonstrate breakdown voltages BVDSS=25V, on-resistances RON=4.9Ωmm, and peak transit frequencies fT=32GHz.

Convergence of Hot-Carrier-Induced Saturation Region Drain Current and On-Resistance Degradation in Drain Extended MOS Transistors

Hot-carrier-induced device degradation in n-type high-voltage drain-extended MOS (DEMOS) devices stressed under high drain voltage and high gate voltage ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Vg</i> ) is investigated. Charge pumping data and technology computer-aided-design simulation results reveal that hot-carrier-induced interface state formation in the gate overlapped shallow trench isolation region is responsible for device degradation. Furthermore, an unexpected high saturation region drain current ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Id</i> (sat)) degradation (close to on-resistance degradation) is observed. The occurrence of quasi-saturation under high <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Vg</i> bias is the cause of significant <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Id</i> (sat) degradation. The results presented in this paper suggest that severe <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Id</i> (sat) degradation may become a reliability concern for devices exhibiting the quasi-saturation phenomenon.

Physical Description of Quasi-Saturation and Impact-Ionization Effects in High-Voltage Drain-Extended MOSFETs

This paper presents a physical description of two specific aspects in drain-extended MOS transistors, i.e., quasi-saturation and impact-ionization effects. The 2-D device simulator Medici provides the physical insights, and both the unique features are originally attributed to the Kirk effect. The transistor dc model is derived from regional analysis of carrier transport in the intrinsic MOS and the drift region. The substrate-current equations, considering extra impact-ionization factors in the drift region, are also rigorously derived. The proposed model is primarily validated by MATLAB program and exhibits excellent scalability for various transistor dimensions, drift-region doping concentration, and voltage-handling capability.

Silicide-block-film effects on high voltage drain-extended MOS transistors

Silicide-block-film effects on drain-extended MOS (DEMOS) transistors were comparatively investigated, by means of different film stack stoichiometric SiO2 and silicon-rich oxide (SRO). The electrical properties of the as-deposited films were evaluated by extracting source/drain series resistance. It was found that the block film plays a role like a field plate, which has significant influence on the electric field beneath. Similar to hot-carrier-injection (HCI) induced degradation for devices, the block film initially charged in fabrication process also strongly affects the device characteristics and limits the safe operating area.

Dependence of Device Structures on Latchup Immunity in a High-Voltage 40-V CMOS Process With Drain-Extended MOSFETs

The dependence of device structures on latchup immunity in a 0.25-mum high-voltage (HV) 40-V CMOS process with drain-extended MOS (DEMOS) transistors has been verified with silicon test chips and investigated with device simulation. Layout parameters such as anode-to-cathode spacing and guard ring width are also investigated to find their impacts on latchup immunity. It was demonstrated that the drain-extended NMOS with a specific isolated device structure can greatly enhance the latchup immunity. The proposed test structures and simulation methodologies can be applied to extract safe and compact design rule for latchup prevention of DEMOS transistors in HV CMOS process

Anomalous Reduction of Hot-Carrier-Induced On-Resistance Degradation in n-Type DEMOS Transistors

Anomalous hot-carrier degradation phenomenon was observed in a 0.5-mum 12-V n-type drain-extended MOS transistors (N-DEMOS) with various n-type drain-drift (NDD) implant dosage. Under the same stress condition, the device with a higher NDD dosage produces a higher substrate current, a slightly higher transconductance degradation, but a lower ON-resistance (RON) degradation. Two degradation mechanisms are identified from the analysis of the electrical data and two-dimensional device simulations. The first mechanism is hot-electron injection in the accumulation region near the junction of the channel and accumulation regions. The second mechanism is hot-hole injection in the accumulation region near the spacer. This injection of hot holes creates a positive-charge trapping in the gate oxide, resulting in negative mirror charges in the accumulation region that reduces RON. The second mechanism is identified to account for the anomalous lower RON degradation

Spatial Distribution of Interface Traps in DeMOS Transistors

The spatial distribution of interface traps in a p-type drain extended MOS transistor is experimentally determined by the analysis of variable base-level charge pumping spectra. The evolution of the interface trap distribution can be monitored as a function of the hot-carrier stress time. A double peaked interface trap density distribution, located in the spacer oxide, is extracted. The interface trap density in the poly overlapped drift region is constant as a function of stress time. No channel degradation is observed.