Abstract
This paper presents a device-circuit co-design approach to achieve a low swing, high speed 1.2-5 V level shifter (LS) using drain extended MOS (DeMOS) transistors for system on chip applications in advance CMOS technologies. Limiting factors of the high-voltage devices during transients are identified and accordingly it is shown that the maximum operating frequency of traditional LS can be increased by at least a factor of two. It is demonstrated that optimization of key device parameters of the DeMOS transistor enhances the maximum clock frequency to more than 1 GHz while preserving the device breakdown voltage and duty cycle of the level shifted signal.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
