Drain Distance Research Articles

Normally-Off AlGaN/GaN/AlGaN Double Heterostructure FETs With a Thick Undoped GaN Gate Layer

In this letter, we report on polarization charge engineering enabling normally-off operation for a double-heterostructure Al0.26Ga0.74N/GaN/Al0.07Ga0.93N-based field effect transistors (DHFETs) using a 35-nm-thick undoped GaN layer underneath the gate metallization. The combined effect of the negative polarization charge induced by the AlGaN back barrier and the undoped GaN gate layer ensures the total depletion of the channel, and provides a positive threshold voltage. The fabricated DHFET exhibits normally-off operation with a threshold voltage of 1.2 V, a maximum drain current density of 370 mA/mm, and a high ON/OFF current ratio of $10^{7}$ , at a gate bias of 7 V. A transistor with gate–drain distance of 6 $\mu \text{m}$ demonstrates 300 V off-state breakdown voltage.

Gate-Source Distance Scaling Effects in H-Terminated Diamond MESFETs

In this paper, an analysis of gate–source and gate–drain scaling effects in MESFETs fabricated on hydrogen-terminated single-crystal diamond films is reported. The experimental results show that a decrease in gate–source spacing can improve the device performance by increasing the device output current density and its transconductance. On the contrary, the gate–drain distance produces less pronounced effects on device performance. Breakdown voltage, knee voltage, and threshold voltage variations due to changes in gate–source and drain–source distances have also been investigated. The obtained results can be used as a design guideline for the layout optimization of H-terminated diamond-based MESFETs.

AlGaN/GaN MOS-HEMTs-on-Si employing sputtered TaN-based electrodes and HfO2 gate insulator

We report on a low specific on-resistance (Ron,sp) of 3.58mΩ-cm2 and a high breakdown voltage of 1.4kV in a CMOS-compatible AlGaN/GaN metal-oxide-semiconductor high-electron-mobility transistor (MOS-HEMT). The MOS-HEMT is on a Si substrate and uses TaN electrodes and a HfO2-gate insulator. The sputtered TaN – a substitute for Au that has low resistivity, high work function, and thermal stability – was applied at room temperature to the gate, source, and drain. In order to obtain a low Ron,sp and high breakdown voltage, sputtering power and post-annealing temperature were optimized by measuring the characteristics of TaN. Using optimized conditions, a sputtering power of 50W, and an annealing temperature of 880°C, we successfully achieved a high on/off current ratio of 6×109 for the proposed AlGaN/GaN MOS-HEMT at a gate–drain distance of 10μm. These results indicate that the TaN process is a promising technique for power-switching GaN devices with CMOS compatibility.

Effect of Bulk-Accumulation on Switching Speed of Dual-Gate a-IGZO TFT-Based Circuits

The effect of bulk accumulation on switching speed of dual-gate amorphous indium–gallium–zinc-oxide thin-film transistor (TFT)-based circuits is investigated. Given that bulk accumulation is achieved by synchronized driving of the top gate (TG) and bottom gate, it can be modulated by varying the length of the TG ( $\textrm {L}_{{{\textrm {TG}}}}$ ) for fixed source–drain distance ( $L$ ). It is confirmed from fabricated ring oscillators that switching speed increases with increasing $\textrm {L}_{{{\textrm {TG}}}}$ for fixed $L$ , verifying that bulk accumulation improves switching speed. However, switching speed drops dramatically when the TG overlaps the source/drain electrodes due to additional parasitic capacitance. TFT-circuits with the longest, but nonoverlapping TGs are demonstrated to exhibit the fastest switching speed; operation frequency exceeding 2.63 MHz for input voltage $\textrm {V}_{{{\textrm {DD}}}}$ of 20 V, which is also the fastest among all inverted staggered amorphous-oxide-semiconductor TFT-based circuits.

High breakdown voltage in AlN/GaN metal–insulator–semiconductor high-electron-mobility transistors

The breakdown characteristics of AlGaN/GaN based metal–insulator–semiconductor high-electron-mobility transistors (MISHEMTs) using a 10 nm thick AlN gate insulator and passivation layer deposited plasma enhanced atomic layer deposition. The AlN was effective in significantly reducing gate leakage current relative to Schottky gate devices and showed only small decreases in drain current during gate lag measurements. The devices exhibited a strong dependence of gate breakdown voltage on source–drain distance, reaching a value of 2000 V for a source–drain distance of 40 μm limited by the measurement instrument. The specific on-state resistance was 1.3 and 10.9 mΩ cm2 for the devices with the gate–drain distance of 7.5 and 37.5 μm, respectively. The saturation drain current was inversely dependent on source–drain distance and the on–off ratios were in excess of 108 due to the low gate leakage current in the MISHEMTs.

1900 V, 1.6 mΩ cm2 AlN/GaN-on-Si power devices realized by local substrate removal

We demonstrate a high-voltage low on-resistance AlN/GaN/AlGaN double heterostructure grown by metal–organic chemical vapor deposition on a silicon (111) substrate using a total buffer thickness of less than 2 µm. A fully scalable local substrate removal technique was developed to dramatically enhance the off-state breakdown voltage of the transistors. The three-terminal breakdown voltage of these devices using a gate–drain distance of 15 µm increased significantly, from 750 V to 1.9 kV, after local substrate removal. The high two-dimensional electron gas carrier density (2.3 × 1013 cm−2) associated with the low sheet resistance enables a record combination of a specific on-resistance (1.6 mΩ cm2) and high breakdown voltage for GaN-on-Si transistors.

Low ohmic contact AlN/GaN HEMTs grown by MOCVD

AlN/GaN high-electron-mobility transistors (HEMTs) on SiC substrates were fabricated by metal-organic chemical vapor deposition (MOCVD) and then characterized. An Si/Ti/Al/Ni/Au stack was used to reduce ohmic contact resistance (0.33 Ω·mm) at a low annealing temperature. The fabricated devices exhibited a maximum drain current density of 1.07 A/mm (VGS = 1 V) and a maximum peak extrinsic transconductance of 340 mS/mm. The off-state breakdown voltage of the device was 64 V with a gate—drain distance of 1.9 μm. The current gain extrinsic cutoff frequency fT and the maximum oscillation frequency fmax were 36 and 80 GHz with a 0.25 μm gate length, respectively.

Bimodal gate-dielectric deposition for improved performance of AlGaN/GaN metal–oxide–semiconductor high-electron-mobility transistors

A bimodal deposition scheme combining radiofrequency magnetron sputtering and plasma enhanced chemical vapour deposition (PECVD) is proposed as a means for improving the performance of GaN-based metal–oxide–semiconductor high-electron-mobility transistors (MOSHEMTs). High-density sputtered-SiO2 is utilized to reduce the gate leakage current and enhance the breakdown voltage while low-density PECVD-SiO2 is employed to buffer the sputtering damage and further increase the drain current by engineering the stress-induced-polarization. Thus-fabricated MOSHEMT exhibited a low leakage current of 4.21 × 10−9 A mm−1 and high breakdown voltage of 634 V for a gate–drain distance of 6 µm, demonstrating the promise of bimodal-SiO2 deposition scheme for the development of GaN-based MOSHEMTs for high-power application.

Characteristics of AlGaN/GaN/AlGaN double heterojunction HEMTs with an improved breakdown voltage

We studied the performance of AlGaN/GaN double heterojunction high electron mobility transistors (DH-HEMTs) with an AlGaN buffer layer, which leads to a higher potential barrier at the backside of the two-dimensional electron gas channel and better carrier confinement. This, remarkably, reduces the drain leakage current and improves the device breakdown voltage. The breakdown voltage of AlGaN/GaN double heterojunction HEMTs (∼100 V) was significantly improved compared to that of conventional AlGaN/GaN HEMTs (∼50 V) for the device with gate dimensions of 0.5 × 100 μm and a gate—drain distance of 1 μm. The DH-HEMTs also demonstrated a maximum output power of 7.78 W/mm, a maximum power-added efficiency of 62.3% and a linear gain of 23 dB at the drain supply voltage of 35 V at 4 GHz.

Sandwich-type gated mechanical break junctions

We introduce a new device architecture for the independent mechanical and electrostatictuning of nanoscale charge transport. In contrast to previous gated mechanicalbreak junctions with suspended source–drain electrodes, the devices presentedhere prevent an electromechanical tuning of the electrode gap by the gate. Thissignificant improvement originates from a direct deposition of the source and the drainelectrodes on the gate dielectric. The plasma-enhanced native oxide on the aluminumgate electrode enables measurements at gate voltages up to 1.8 V at cryogenictemperatures. Throughout the bending-controlled tuning of the source–drain distance, theelectrical continuity of the gate electrode is maintained. A nanoscale island in theCoulomb blockade regime serves as a first experimental test system for the devices, inwhich the mechanical and electrical control of charge transport is demonstrated.

Scaling laws for nanoFET sensors

The sensitive conductance change of semiconductor nanowires and carbon nanotubes inresponse to the binding of charged molecules provides a novel sensing modality which isgenerally denoted as nanoFET sensors. In this paper, we study the scaling laws ofnanoplate FET sensors by simplifying nanoplates as random resistor networks withmolecular receptors sitting on lattice sites. Nanowire/tube FETs are included as thelimiting cases where the device width goes small. Computer simulations show that the fieldeffect strength exerted by the binding molecules has significant impact on the scalingbehaviors. When the field effect strength is small, nanoFETs have little size and shapedependence. In contrast, when the field effect strength becomes stronger, thereexists a lower detection threshold for charge accumulation FETs and an upperdetection threshold for charge depletion FET sensors. At these thresholds, thenanoFET devices undergo a transition between low and large sensitivities. Thesethresholds may set the detection limits of nanoFET sensors, while they could beeliminated by designing devices with very short source–drain distance and large width.

Non-percolating nanotube networks for thin film transistors: A pathway to channel length reduction

This study outlines a method to increase the transconductance of thin film transistors (TFTs) by assembling non-percolating random arrays of carbon nanotubes. It represents an effective, simple tool to substantially reduce the transistor channel length, thus increase transconductance, without lessening the on/off ratio. When non-percolating arrays of carbon nanotubes are linked via a semiconducting overlay, the majority of current paths between source and drain follow the highly conducting nanotubes with short, switchable semiconducting links completing the circuit. This field-induced percolating network allows for high transconductance with relatively large source—drain distance. Thus, transistors can be manufactured inexpensively by commercially available techniques using a variety of available semiconductors.

Simulation and optimization of EJ-MOSFETs

Electrically variable shallow junction (EJ) MOSFETs with a channel length of 50 nm, source–drain distances between 150 nm and 9 μm, and different channel dopings have been systematically investigated by means of 2D device simulation. SOI EJ-MOSFETs with a highly doped channel show a subthreshold behavior similar to the comparable bulk version. By decreasing the source–drain distance down to 150 nm and lowering the channel doping the on-currents of EJ-MOSFETs can be increased by more than two orders of magnitude.

Transport properties of carrier-injected DNA

We have studied electric properties of carrier-injected deoxyribonucleic acid (DNA) molecules. First, a current (ICA) through a single DNA molecule was measured by the two-probe dc method with varying a distance between a cathode and an anode (dCA). The ICA–dCA curve showed that the current rapidly decreased with increasing dCA (ICA≲0.1 nA for dCA≳6 nm) according to a hopping model. Next, we measured electric properties of DNA injected carriers by two methods; a field effect transistor (FET) arrangement and a chemical doping. In the FET arrangement, we set three electrodes on a single DNA molecule as source, drain, and gate electrodes with a source–drain distance (dDS)∼20 nm. When a voltage was applied to the gate, the source–drain current (IDS) could be detected to be 0.5–2 nA. This showed that charge injection with the FET arrangement would yield a carrier transportation through DNA at least dDS∼20 nm. In order to flow a current through DNA over a distance ∼100 μm, we synthesized the DNA-acceptor cross-linked derivatives (DACD). In the structure of DACD, DNA molecules, which were attached acceptor molecules at guanine sites specifically, were cross-linked by linker molecules. We can modulate the carrier concentration in DACD with changing a guanine–cytosine pair content (pGC) in a DNA double strand. We measured the current–voltage curves of DACD for various pGC. The conductivity of DACD increased nonlinearly with an increase in pGC. We explained this behavior using a percolation model, so that a two-dimensional conductive network would form in DACD.

Vertical field effect transistors realized by cleaved-edge overgrowth

We present a brief survey of vertical transistor devices fabricated by the cleaved-edge overgrowth technique. Different device types are realized using different transistor substrates grown by molecular beam epitaxy. These substrates mainly vary in the layer sequence and thickness between the source/drain contacts. Common to all designs is the vertical gate structure overgrown on a cleavage plane of the substrates. By biasing the gate a two-dimensional electron system of tunable density is induced between source/drain. We study the DC transport properties of long channel (source–drain distance ∼1 μm ) as well as short-channel (source–drain distance ∼50 nm ) devices. Also the choice of the source/drain isolation (a superlattice or a p +- δ-doping or a heterobarrier) affects the characteristic device behavior.

Impact ionisation in GaAs planar-doped barrier structures grown by molecular layer epitaxy

The I–V characteristics and substrate current of GaAs planar-doped barrier (PDB) n+-i-p+-i-n+ structures with various barrier heights (0.5–0.8 V) grown by molecular layer epitaxy (MLE) have been measured at temperatures ranging from 77 to 296 K. The measurement was carried out at the constant source–drain distance of 1000 Å. It is found that an abrupt increase in the drain current occurs, in the high barrier (>0.73 V) PDB structures at a threshold bias voltage VTH. The value of VTH decreases from 3.1 to 2.7 V with increasing temperature from 77 to 296 K, and the coefficient is –1.8 mV/K. The ratio of VTH and GaAs bandgap Eg is obtained to be eVTH/Eg ≈ 2. The mechanism of the abrupt increase in the drain current is attributed to the effects of ballistic electron transport and the lowering of the potential barrier by the accumulation of impact-ionisation-generated holes at the p+ plane. Furthermore, this mechanism is confirmed by the results of photocurrent measurements, in which holes are generated by incident light. The obtained results have important implications for the design of the barrier height in PDB structures and other devices having thin potential barriers.

Process technology for InGaAs/InAlAs modulation doped field effect transistors on InP substrates

We present a process for fabricating lattice-matched InGaAs/InAlAs modulation doped field effect transistors (MODFETs) on InP wafers including molecular beam epitaxial growth of a high electron mobility transistor structure consisting of In0.53Ga0.47As and In0.52Al0.48As layers, and electron-beam lithography for gate definition. For selective gate recessing we investigated both wet and dry etch processes. Viable procedures have been found with a citric acid: H2O2:H2O wet etching solution and with an HBr/Ar gas mixture for reactive ion etching (RIE). The selectivities obtained for InGaAs with respect to InAlAs were 14:1 for the wet etchant and 6.7:1 for RIE. Another crucial process step is the MODFET isolation. Earlier work by other groups has shown that implant isolation is difficult on InGaAs [S. J. Pearton et al., Mater. Res. Soc. Symp. Proc. 144, 433 (1989)]. Therefore, we studied both oxygen ion implantation as well as wet-chemical mesa etching for device isolation on the same wafer. Although the isolation sheet resistance achieved with ion implantation is inferior to that obtained in a mesa process, we found similar MODFET performance for both approaches. For devices with a 0.3-μm gate length and 1.3-μm source–drain distance, a transconductance of more than 600 mS/mm and threshold voltages of −1.3 and −0.6 V for wet and dry recessed transistors, respectively, were obtained. Wafer mapping measurements showed that the MODFET data are uniform over an entire 2-in. wafer and also from wafer-to-wafer within a batch.

Dynamic land capability model: a case history

A computer simulation approach has been developed that quantifies land capability in terms of crop productivity under different conditions of climate, soil, drainage or irrigation and farm management. This model deals with: (i) the dates and number of days in spring when soil moisture content falls sufficiently to permit soil cultivation and sowing or planting (farm management aspect); (ii) duration of germination and time of emergence in relation to soil moisture and temperature; (iii), water uptake, development, growth and harvest of the crop; (iv) number and time of soil workable days available for the harvest of root crops in autumn (farm management aspect). The model was applied to compute effects of land drainage (15 combinations of drain depth and distance) on the yield of potatoes and spring cereals growing during 30 years (1952-81) on eight different soil types in the Netherlands. The outcome of this study was used as a basis for a nationwide system for evaluating the effects of soil and drainage upon crop yields. The methodology of the integrated model approach can be applied in other climates for a variety of crops growing on different soil types. It can be used to evaluate not only drainage effects on yield, but also those of irrigation and soil improvement. The approach is applicable to land evaluation studies in general.

The performance of surface and subsurface drainage on heavy clay soils in Yugoslavia.

The soils of the Sava River basin (Yugoslavia) have a permeable topsoil of about 0.3 m depth, which overlies an impermeable subsoil. During rainfall, horizontal flow through the topsoil occurs. Appropriate formulae for steady and non-steady flow have been derived, which, together with field observations on field accessibility, have permitted the determination of drainage requirements. In selecting the best drainage system the projected mechanization of agriculture in the area has been considered. Partly for this reason, partly because it provides better drainage during reclamation and in the first year of cropping, and partly for long-term economic reasons (initial costs are higher), subsurface drainage (1.0-1.2 m depth and 15 m drain distance) is preferred to surface drainage. Factors determining peak discharges of field drains are discussed. (Abstract retrieved from CAB Abstracts by CABI’s permission)

Salaojituskoetoiminnasta Suomessa

Salaojituskoetoiminnasta Suomessa