Drain Current Of Transistor Research Articles

Electrically Controlled High Sensitivity Strain Modulation in MoS2 Field-Effect Transistors via a Piezoelectric Thin Film on Silicon Substrates.

Strain can modulate bandgap and carrier mobilities in two-dimensional (2D) materials. Conventional strain-application methodologies relying on flexible/patterned/nanoindented substrates are limited by low thermal tolerance, poor tunability, and/or scalability. Here, we leverage the converse piezoelectric effect to electrically generate and control strain transfer from a piezoelectric thin film to electromechanically coupled 2D MoS2. Electrical bias polarity change across the piezo film tunes the nature of strain transferred to MoS2 from compressive (∼0.23%) to tensile (∼0.14%) as verified through Raman and photoluminescence spectroscopies and substantiated by density functional theory calculations. The device architecture, on silicon substrate, integrates an MoS2 field-effect transistor on a metal-piezoelectric-metal stack enabling strain modulation of transistor drain current (130×), on/off ratio (150×), and mobility (1.19×) with high precision, reversibility, and resolution. Large, tunable tensile (1056) and compressive (-1498) strain gauge factors, electrical strain modulation, and high thermal tolerance promise facile integration with silicon-based CMOS and micro-electromechanical systems.

Influence of RF power in the sputter deposition of amorphous InGaZnO film on the transient drain current of amorphous InGaZnO thin-film transistors

The device electrical and transient current characteristics of the amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistors (TFTs) are comprehensively investigated according to the radio-frequency (RF) power during the sputter-deposition of IGZO active film. The RF power dependencies of the oxygen vacancy (VO) concentration in IGZO and the surface morphology of IGZO film are analyzed through X-ray photoelectron spectroscopy (XPS) and atomic force microscope (AFM). According to the RF power change in the range of 100 ∼ 250 W, the optimal point in terms of threshold voltage (VT), ON current (Ion), field-effect mobility in the linear region (μFE_lin), hysteresis voltage (VHys), and the VT shift under current stress (ΔVT) is found to be 200 W. The existence of the optimal power condition originates from the RF-power dependencies of the electron carrier concentration, the density of electron traps in gate insulator (GI), and the interface trap density related to surface roughness.Furthermore, compared to the direct current (DC) current stress (CS) condition, it is found that when VGS rises rapidly, a total transient current ΔID can be decomposed into three components, i.e., ΔIOS, ΔIBOOST, ΔIDEG. While ΔIOS is attributed to the non-quasi static Fermi-level rising, ΔIBOOST and ΔIDEG result from the donor creation in IGZO and the electron trapping into GI and interface. Noticeably, the occurrence level of each component changes sensitively according to RF power.Our result suggests that the 200 W device has the least overshoot of transient current and shows the best reliability in terms of deterioration due to transient current characteristics.

Development of Direct Electron Transfer-Type Extended Gate Field Effect Transistor Enzymatic Sensors for Metabolite Detection.

In this work, direct electron transfer (DET)-type extended gate field effect transistor (EGFET) enzymatic sensors were developed by employing DET-type or quasi-DET-type enzymes to detect glucose or lactate in both 100 mM potassium phosphate buffer and artificial sweat. The system employed either a DET-type glucose dehydrogenase or a quasi-DET-type lactate oxidase, the latter of which was a mutant enzyme with suppressed oxidase activity and modified with amine-reactive phenazine ethosulfate. These enzymes were immobilized on the extended gate electrodes. Changes in the measured transistor drain current (ID) resulting from changes to the working electrode junction potential (φ) were observed as glucose and lactate concentrations were varied. Calibration curves were generated for both absolute measured ID and ΔID (normalized to a blank solution containing no substrate) to account for variations in enzyme immobilization and conjugation to the mediator and variations in reference electrode potential. This work resulted in a limit of detection of 53.9 μM (based on ID) for glucose and 2.12 mM (based on ID) for lactate, respectively. The DET-type and Quasi-DET-type EGFET enzymatic sensor was then modeled using the case of the lactate sensor as an equivalent circuit to validate the principle of sensor operation being driven through OCP changes caused by the substrate-enzyme interaction. The model showed slight deviation from collected empirical data with 7.3% error for the slope and 8.6% error for the y-intercept.

Improved RFET Performance Using Dual-Aluminum-Contact (DAC)

The reconfigurable field effect transistors (RFET) enable the integration of MOS-type transistors (N-type and P-type) in a single device. The programming gate voltage (VPG) controls the transistor type [1]. A greater area efficiency in logic circuits can be obtained, due to the possible different logic operation, such as NAND to NOR in a single circuit [2 - 3]. Others application include the use of RFET in circuits for security reason in order to avoid the reverse engineering [4]. Figure 1 (A) and (B) show a special type of RFET called BESOI MOSFET that will be one of the devices used in this work.Many conventional RFETs contain NiSi source/drain (S/D) contacts, or other contacts with mid-gap S/D material, providing a symmetrical current between holes and electrons. However such contacts decrease injection of current [5 - 7]. Devices based on dual-doping (DD), provided a significant improvement in the current level, in addition to the ease fabrication due to the absence of the silicidation process, such technology cannot act in doping-free CMOS processes [6] [8]. Figure 2 shows the drain current as a function of the control gate voltage (IDS -VCG) for the BESOI MOSFET.This work presents a new proposal for a dual-contact S/D (DC) RFET, without the presence of DD regions and doping process, enabling dopants-free CMOS processes, using only S/D aluminum contacts, performed through Sentaurus TCAD simulations [9].Recently in the Integrable Systems Laboratory of the University of São Paulo (LSI-USP), two RFET with aluminum S/D contacts were reported. Both presented a high current for only one type of carrier (holes or electrons) [10 - 13]. The BESOI MOSFET conducts current through its back interface, where the channel between S/D contacts is formed by the bias of the programming gate (VPG), thus its operating mode is divided into P-type (VPG < 0 ) and N-type (VPG > 0). The transistor drain current is controlled by control gate voltage (VCG) [5] [10 - 11].The Figure 3 shows the drain current balanced as a function of the control gate voltage (ID -VCG), for aluminum BESOI MOSFET’s with and without annealing process (W/A, Wo/A) after the metal deposition [10 - 11]. Using both BE SOI MOSFET with S/D aluminum contact, without process doping, a new RFET Dual Aluminum Contact (DAC) is shown Figure 4.The challenge the design is to flow of current (holes) through the outer contact (W/A contact), due to the influence of the inner schottky low-barrier aluminum contact (Wo/A contact) near to the back interface. Figure 5 shows the carrier density as a function of the depth of the silicon under the inner contact, for different silicon thicknesses (tSi) and fixed programming gate voltage (VPG). The high concentration of electrons near to the inner contact, provided an ohmic contact for electrons [11], however near the back interface, an increasing concentration of holes, due to VPG. Increasing the tSi reduces the influence of charges near the back interface, for tSi=30nm the current flow between the outer contact is possible. However, increasing the tSi decreases the efficiency of the control gate, added to the high electric field in back interface increases IOFF (similar effect described for FD SOI [14]). The Figure 6 shows the drain current as a function of the control gate voltage of BESOI nMOSFET with tSi = 30nm. Such effect can be mitigated, optimizing the coupling the gates. Figure 7 shows the final proposal of the BESOI MOSFET DAC.Figure 8 shows the IDS-VCG for different thicknesses in the S/D contacts (tsi cont). As shown in Figure 5, a greater thickness in the contacts makes possible a smaller influence of the inner contact near the back interface, allowing greater concentrations of gaps, so consequently there is an increase in the p-mode current. However, increasing the thickness of the contacts promotes a reduction in the electron current, due to the increase in the series resistance in inner contact in n-mode.Figure 9 presents the ID-VCG for different VPG bias for the DAC BESOI MOSFET (A) and NiSi BESOI MOSFET (B). Using the DAC BESOI MOSFET, an increase in current was obtained in relation to the NiSi contact (900% in n-type and 300% in p-type), without the addition of doping regions (dual-doping) and using a single contact metal (Aluminum). Figure 1

Low temperature multi-differential operational amplifier

A multi-differential operational amplifier, called OAmp3, designed for operation at temperatures up to minus 197 °С and developed on bipolar transistors and junction field-effect transistors of the master slice array МН2ХА030, is considered in the article. The circuitry features of the OAmp3 allow, due to the use of various negative feedback circuits, to implement a set of functions necessary for signal processing on a single amplifier: amplification (or current – voltage conversion), filtering, shift of the constant output voltage level. The performed measurements of OAmp3, connected as instrumentation amplifier circuit, showed that all manufactured products retain their performance in the temperature range from minus 150 °С to 20 °С, and individual samples – at minus 197 °С. It was found that the main reason for the loss of OAmp3 performance is an increase of the resistance of semiconductor resistors by almost 5.4 times at minus 197 °С compared to normal conditions and decrease in the junction field-effect transistor drain current. Together, these factors lead to decrease in the current consumption of the OAmp3 by almost 31 times at minus 180 °С compared to normal conditions. To reduce the temperature dependence of the current consumption and, thus, save the OAmp3 operability at low temperatures without changing the technological route of integrated circuits manufacturing, it is proposed to replace high-resistance semiconductor resistors with “pinch-resistors” formed on a small-signal p-junction field-effect transistor. The article presents the OAmp3 connection circuit in the form of an instrumental amplifier, the method and results of low-temperature measurements of experimental samples.

An Approach for Drain Current Modeling Including Quantum Mechanical Effects for a DMDG Junctionless Field Effect Nanowire Transistor

This paper presents the effects of quantum confinements on the surface potential, threshold voltage, drain current, transconductance, and drain conductance of a Dual Material Double Gate Junctionless Field Effect Nanowire Transistor (DMDG-JLFENT). The carrier energy quantization on the threshold voltage of a DMDG-JLFENT is modeled, and subsequently, other parameters like drain current were analytically presented. The QME considered here is obtained under the quantum confinement condition for an ultra-thin channel, i.e., below 10 nm of Si thickness. The threshold voltage shift due to QME can be used as a quantum correction term for compact modeling of junctionless transistors. The analytical model proposed for surface potential, threshold voltage, drain current, transconductance, and drain conductance were verified by TCAD 3-D quantum simulation results which makes it suitable for SPICE compact modeling.

Introducing effective temperature into Arrhenius equation with Meyer-Neldel rule for describing both Arrhenius and non-Arrhenius dependent drain current of amorphous InGaZnO TFTs

The drain current of the amorphous InGaZnO thin-film transistors (TFTs) shows the Arrhenius and the non-Arrhenius dependence at the high temperature and the low temperature respectively. The gate-voltage-dependent effective temperature is introduced into the Arrhenius equation. Considering the normal Meyer-Neldel (MN) rule and the inverse MN rule, the equation successfully describes both the Arrhenius and the non-Arrhenius dependent drain current at the low and the high gate voltage. The calculated results of the equation are verified by the available experimental data of the amorphous La-doped InZnO TFT and the amorphous InGaZnO (InO3:Ga2O3:ZnO = 1:1:1 mol%) TFT.

Process validation test of CNTFET using Stanford model

ABSTRACT Process validation test (PVT) helps to predict the response of a device to various figure of merit (FOM) parameters, such as diameter (process), supply voltage, and temperature. In this paper, the Stanford model is modified to investigate the effect of temperature, nanotube diameter, etc. on the current-voltage characteristics, drain current, transconductance, threshold voltage, subthreshold swing, and conductance of Carbon Nanotube Field Effect Transistors (CNTFETs). To study different parameters in terms of temperature in CNTFETs, we simulate different circuits by adding temperature-dependent voltage/current equations and defining temperature as a parameter in the Stanford model. The results show that an increase in temperature results in higher subthreshold swing, lower on/off current ratio, and lower threshold voltage. Moreover, by adding the variable diameter to the model, we examine its effect on different CNTFET parameters. As diameter increases, both the on/off current ratio and subthreshold swing increase, so the net effect is almost the same. CNTFET noise model is translated in Verilog-A, and then implemented in the ADS simulator. The results show that the shot noise is more noticeable at high frequencies and the flicker noise at low frequencies. Moreover, the noise figure of CNTFET is higher at lower frequencies.

Boosting the Performance of Liquid‐Gated Nanotransistor Biosensors Using Single‐Trap Phenomena

AbstractIn small‐area transistors, the trapping/detrapping of charge carriers to/from a single trap located in the gate oxide near the Si/SiO2 interface leads to the discrete switching of the transistor drain current, known as single‐trap phenomena (STP), resulting in random telegraph signals. Utilizing the STP‐approach, liquid‐gated (LG) nanowire (NW) field‐effect transistor biosensors have recently been proposed for ultimate biosensing with enhanced sensitivity. In this study, the impact of channel doping concentration on the capture process of charge carriers by a single trap in LG silicon NW structures is investigated. A significant effect of the channel doping concentration on the single‐trap dynamic is revealed. To understand the mechanism behind unusual capture time behavior compared to that predicted by the classical Shockley–Read–Hall theory, an analytical model based on the rigorous description of the additional energy barrier that charge carriers have to overcome to be captured by the trap at different gate voltages is developed. The enhancement of the sensitivity for single‐trap phenomena biosensing with an increase of the channel doping concentration is explained within the framework of the proposed analytical model. The results open prospects for the development of advanced single trap‐based devices.

Charge-Based Model for the Drain-Current Variability in Organic Thin-Film Transistors Due to Carrier-Number and Correlated- Mobility Fluctuation

In this study, a consistent analytical charge-based model for the bias-dependent variability of the drain current of organic thin-film transistors is presented. The proposed model combines both charge-carrier-number-fluctuation effects and correlated-mobility-fluctuation effects to predict the drain-current variation and is verified using experimental data acquired from a statistical population of organic transistors with various channel dimensions, fabricated on flexible polymeric substrates in the coplanar or the staggered device architecture.

Impact evaluation of DC operating condition on DPD linearizability and power efficiency in GaN-based power amplifiers

AbstractThe paper presents the results of studies on the effect of transistor DC operating conditions on GaN power amplifiers’ (PAs) power efficiency and linearity improved by digital predistortion (DPD). The single-ended 10 W (ISM2.45 GHz) and 150 W (3.4/3.6 GHz) GaN HEMT PAs excited by wideband LTE20 E-TM1.1 signal were tested. To check the applicability of the small-signal approach for designing of LTE signals’ PAs, the 150 W PA using transistor model extracted from S-parameters measured at the properly selected operating points was designed. The conventional DPD based on the indirect learning architecture and the memory polynomial model of PA non-linearity was implemented. The results of the research show that in case of class A and B PAs operating up to several dozen watts, an additional improvement in adjacent channel leakage ratio (ACLR) of the order of a few dB only by an increase in the quiescent drain current of PA transistor can be achieved. However, a noticeable ACLR improvement with a coincident increase in power-added efficiency (PAE) can be obtained by choosing the compromise DC operating point and using DPD. In the case of high-PAs, the linearity and efficiency are strongly dependent on the load of a transistor, thus the role of DPD is significantly increased.

A Holistic Approach on Junctionless Dual Material Double Gate (DMDG) MOSFET with High k Gate Stack for Low Power Digital Applications

The 2D analytical models for electrostatic potential, threshold voltage, subthreshold swing, Drain Induced Barrier Lowering (DIBL) and drain current of the Dual Material Double Gate junctionless transistor with high k gate structure is revealed. The electric field is obtained by solving Poisson equation with the help of parabolic approximation technique. The high k gate stack engineered (JL DMDG stack MOSFET) exaggerate the ION current of 10−4 (A/μm) and IOFF current of 10−14(A/μm) gives a remarkable amount of leakage current reduction. The short channel effects are quashed with the symmetric high k gate stack structure to a good extent. The device characteristics have been analyzed for various different high k materials. The significant outcomes of analytical solutions are mapped with the numerical solutions from Synopsys TCAD device simulator to affirm and validate the device structure. The JL DMDG Stack MOSFET based inverter circuit was also implemented to empower the device performance in digital applications. The voltage transfer characteristics, noise margin, delay and power dissipation of the JL DMDG stack MOSFET inverter circuit is assessed through numerical simulator with the help of Verilog-A language show substantial improvement due to this gate stack engineering model.

Chromium(III) Sensor Using Ion Selective Membrane Immobilized on FET for Ground Water Pollution

Anthropogenic industrialization related activities contribute to rising concentrations of heavy metal in the environment. This unprecedented deterioration of water quality by industrial effluents raises severe global health concern to both humanity and the ecosystem. Chromium, the 21st most abundant element on the earth’s crust, is extensively used in steel manufacturing, leather tanning, electroplating, paint and alloy manufacturing industries. The effluents released pollute water with Cr(III); classified as a group III carcinogen causing genotoxicity to flora and fauna. Hence water quality monitoring by detecting heavy metal concentration in tap water, canned liquid food items, etc will be of immense application if the sensor is affordable and equipped with simple user interface. Conventional methods like ICP-MS and AAS demand time, expense and complex equipments which are beyond the scope of daily use. This work reports detection of Cr(III) employing Field Effect Transistor with Ion Selective Membrane on the gate electrode.The gate metal is extended and terminates in a two sensing electrode configuration modified with Poly Vinyl Chloride based sensing material.It is composed of an ionophore which binds with target analyte; consequently leading to a change in the transistor drain current. High sensitivity, selectivity and fast response time were observed in the pH range 3- 5 beyond which Cr forms hydroxyl complexes.The effective voltage at gate dielectric is a function of the concentration of Cr(III) ions in the test solution dropped on the sensing membrane. The device exhibits increasing trend of current gain with increase in concentration of the target ion as depicted in the plot. Hence, our simple novel biosensor can be calibrated to realize a cost effective, portable device to measure concentration of Cr(III) in real time drinking water quality monitoring or be integrated into food processing systems or even in medical diagnostics. Figure 1

Current Enhancement and Bipolar Current Modulation of Top-Gate Transistors Based on Monolayer MoS2 on Three-Layer W xMo1- xS2.

We demonstrated the top-gate transistors composed of monolayer MoS2 grown on three-layer alloys Mo xW1- xS2 prepared by sequential sulfurization of predeposited transition metal films. The elemental mapping of the alloy indicates a uniform distribution of both cations Mo and W in the grown samples. Surprisingly, we find that the drain current of transistors could be enhanced by 2 orders of magnitude as the composition of Mo increases, whereas the gate-controlled current modulation turns bipolar and ultimately vanishes. These features might originate from the formation of in-gap defect states, with modest activation energy for transport and moderate hopping probability for current conduction, or a reduced electronic band gap of the conducting channel because of strain.

Influence of metal contact on the performance enhancement of monolayer MoS2 transistor

This paper investigate the impact of metal contact on the performance of 10 nm channel length monolayer MoS2 transistor. We studied the interface charge density between various metal and MoS2 semiconductor interface using Atomistic Tool Kit (ATK). The electrical characteristics of MoS2 transistor is studied using extracted interface charge density. Non-equilibrium Green's function with mode space (NEGF_MS) is used to model the electron transport behavior of the monolayer MoS2 transistor for numerical simulation. We also investigate the impact of gate work function on drain characteristics, whereas the work function of gate metal has influenced the off-current. The drain current of monolayer MoS2 transistor with Scandium source/drain contact and Niobium as gate contact exhibits 1.92 times higher current than gold metal contact with reported field effect mobility of 649 cm2/V.

Modeling drain current of indium zinc oxide thin film transistors prepared by solution deposition technique

Indium zinc oxide (IZO) thin film transistor (TFT) deposited by solution method is of considerable technological interest as it is a key component for the fabrication of flexible and cheap transparent electronic devices. To obtain a principal understanding of physical properties of solution-processed IZO TFT, a new drain current model that account for the charge transport is proposed. The formulation is developed by incorporating the effect of gate voltage on mobility and threshold voltage with the carrier charges. It is demonstrated that in IZO TFTs the below threshold regime should be divided into two sections: EC − EF > 3kT and EC − EF ≤ 3kT, where kT is the thermal energy, EF and EC represent the Fermi level and the conduction band edge, respectively. Additionally, in order to describe conduction mechanisms more accurately, the extended mobility edge model is conjoined, which can also get rid of the complicated and lengthy computations. The good agreement between measured and calculated results confirms the efficiency of this model for the design of integrated large-area thin film circuits.

A theoretical study on the temperature-dependent RF performance of a SiC MESFET

ABSTRACTThe impact of ambient temperature on the drain current of a SiC Metal-Semiconductor Field Effect Transistor (MESFET) has been studied theoretically assuming the device is operating under two-region model. This study has been extended to explore the effect of temperature on other device parameters i.e. drain resistance, mutual conductance, cut-off frequency and maximum operating frequency. It is observed that the overall performance of the device in terms of these parameters degrades as the device temperature is enhanced. In addition, the device performance is also studied incorporating self-heating effect applicable at higher drain field. The results calculated using this work are compared with the experimental data reported earlier and a good agreement has been found.

The modified alpha power law based model of statistical fluctuation in nanometer FGMOSFET

The modified alpha power law based model of statistical fluctuation in drain current of an unconventional Metal Oxide Semiconductor Field Effect Transistor namely Floating-Gate Metal Oxide Semicond...

Comparison of purity in single walled carbon nanotube gas detectors with Pd and Ti electrodes using low frequency noise techniques

This work deals with oxide traps properties of single walled carbon nanotubes (SWCNTs) based gas sensors using Random telegraph signals (RTS) and low frequency (LF) noise techniques. RTS signals are two or more levels switching events that we observe measuring the drain current of transistors with Ti (RTS1) and Pd (RTS2) contacts. RTS noise is analyzed in time and frequency domains. Time domain analysis allows us to identifying slow traps (three traps) responsible to RTS noises (energetic position and cross capture section). These traps undetectable by other techniques, e.g. deep level transient spectroscopy (DLTS) technique, are localized in the gate oxide region. The spatial localization of the three traps in the SWCNT/SiO2 interface are determined using numerical simulations (yTrap1 ≈0.6nm, yTrap2 ≈0.9nm and yTrap3 ≈0.3nm). (RTS1) noise is attributed to trap1 and (RTS2) to traps 2 and 3. From RTS analysis in frequency domain, are able to extract the cut-off frequencies of a single trap even at very low frequencies (for RTS1 noise fc=10Hz (trap1) and for RTS2 noise fc1=4Hz (trap2), fc2=50Hz (trap 3)). These results are in good agreement with those obtained by analysis in time domain and confirm the localization of each trap from the SWCNT/SiO2 interface. This is the first time that this kind of studies is performed on CNTFETs used as gas sensors and gives us some interesting hints on the potential phenomena related to these new generation of carbon based nanomaterials based devices in the field of electronics.

Charge transport study of P3HT blended MoS2

Hybrid organic–inorganic hetero-structures, especially inorganic two-dimensional (2D) materials and organic semiconductors are attracting great attention for optoelectronic applications. The quantum confinement effects of 2D materials and their low-cost processing and high performance in devices enable a high degree of tunable optoelectronic properties for these heterostructure. Herein, we attempted to doped poly(3-hexylthiophene) (P3HT) with 2D nanosheets of Molybdenum sulfide (MoS2) to improve its mobility. We synthesized 2D MoS2 nanosheets using ultrasonication method for exfoliation of MoS2. The successful synthesis of 2D MoS2 monolayers is evidenced through substantial characterization viz Atomic Force Microscopy and UV-visible Spectroscopy. The thickness of these nanosheets varies between 8 and 10 nm. The doping of MoS2 significantly improved the mobility of the P3HT as evident from the enhanced drain current of organic field effect transistors (OFET) as compared to the undoped P3HT.