Drain Current Of Transistor Research Articles

Current conduction models in the high temperature single-electron transistor

Single-electron transistor drain current is studied as a function of the temperature. A current conduction model based on the physical properties of the tunnel junctions is proposed to explain the discrepancies observed at high temperature between the experimental data and Monte Carlo simulations. The extension of the model includes a thermionic and a field assisted emission component. A demonstration of this approach is presented for a metallic single-electron transistor characterized up to 430 K.

A percolation model for random telegraph signals in metal-oxide-silicon field effect transistor drain current

Random telegraph signals (RTS) typically do not follow a simple model with uniform charge distributions and electron trapping causing a change in the average threshold voltage. Most often RTS with amplitudes greater than one electron are observed. These signals do not have a normal or Gaussian amplitude distribution. A model is presented here for RTS where electron trapping modulates preferential current paths in the device active region.

On the possibility of degradation-free field effect transistors

Time-dependent change in threshold voltage, due to generation of interface/bulk traps, degrades drain current of field effect transistors. In this paper, we show—both theoretically and experimentally—the intriguing possibility of designing degradation-free transistors (with time-invariant drain current), where the degradation in threshold voltage is exactly compensated by improvement in mobility. Such transistors would reduce parametric reliability being a key concern for supply voltage scaling and thereby improve integrated circuit performance by minimizing the guard band voltage used in very large scale integrated circuit design.

Impact of axial strain on drain current of carbon-nanotube field-effect transistors with doped junctions

The effect of axial strain on the performance of carbon-nanotube field-effect transistors with doped junctions is studied. When the diameter of carbon nanotubes (CNTs) is less than 1.5nm, the decrease of the off-current by axial strain occurs together with the decrease of on-current. However, if the diameter of CNTs is larger than 1.5nm, axial strain is effective for decreasing off-current while enhancing the on-current at the same time. The decrease of off-current is due to the opening of the bandgap by axial strain, whereas the increase of on-current is attributable to current flowing through the first excited state.

Traps identification in silicon nanocrystals memories by low noise technique

This work reports the extraction of oxide traps properties of n-metal–oxide–semiconductor field-effect transistors with W × L = 0.5 × 0.1 μm 2 using random telegraph signals (RTS) techniques. RTS study of nc-Si has been performed on thin tunnel oxides from 0.8 to 2.0 nm. RTS signals were two or more levels switching events observed on the drain current of transistors with and without nc-Si. The simple two levels RTS 1 noise was observed on samples without nc-Si. On transistors with nc-Si we distinguish two different RTSs (RTS 2 and RTS 3). RTS signal variations with temperature have shown that there's three slow interfacial traps located at E c — 0.26 eV (trap1), E c — 0.23 eV (trap2) and E c — 0.2 eV (trap3). The spatial localization of traps 1, 2 and 3 from the Si–SiO 2 interface are determined using numerical simulations ( x Trap1 ≈ 0.6 nm, x Trap2 ≈ 0.8 nm and x Trap3 ≈ 0.4 nm). RTS noise observed on these devices is attributed to traps localized precisely at the interface thermal oxide/deposited control oxide. (RTS 1) noise is attributed to trap1 and (RTS 2, RTS 3) to traps 2 and 3. From RTS analysis in frequency domain, we extract the power spectrum density of the drain current noise (PSD). From these PSDs we have measured the cut-off frequencies of a single trap even at very low frequencies (for RTS 1 noise f c = 5 Hz (trap1) and for RTS 2 noise f c1 = 2 Hz (trap2), f c2 = 130 Hz (trap3)). These results are in good agreement with those obtained by analysis in time domain and confirm the localization of each trap from the Si–SiO 2 interface.

Using residue sums to estimate high‐order Fourier harmonics of piecewise‐continuous transcendental functions: Application to Class A‐, B‐ and F‐type amplifier circuits

AbstractA discrete fast‐Fourier transform (DFFT) is the preferred method of choice for the rapid evaluation of a set of harmonics of a piecewise‐continuous and periodic transcendental form. For large sets of Fourier components specified to some stringent error criterion, the approach becomes increasingly unattractive owing to the presence of round‐off errors that result from the switching of one transcendental form to another. As an alternative, it might be wondered whether the high‐frequency components can be more efficiently estimated by employing a combination of residue sums and boundary integrals in the complex plane z = Reiωt, where ω is the fundamental frequency and R = ∣z∣.The starting point is the construction of suitable contours that divide the complex plane into a number of sectors in accordance with the number of intervals of smooth behaviour of a periodic piecewise‐continuous real function along ∣z∣ = 1. Each sector encompasses the analytic extension of a real transcendental function on ∣z∣ = 1 to yield p(z)T(f(z)), where T(ζ) is meromorphic and p(z), f(z) are Laurent series. Fourier coefficients are subsequently expressed in terms of residue series and constant‐phase boundary integrals from each of the various sectors associated with a given p(z)T(f(z)). This approach is applied to the model for the drain current of a field effect transistor (FET), where in this case T(ζ) = tanh(ζ), which is subject to the modes of operation: ‘Class A’, ‘Class B’ and approximate ‘Class F’. In contrast to Classes A and B, the Fourier coefficients in the ‘Class F’ drain current decay slowly with frequency, suggesting that this mode might be more suitably analysed using a combined DFFT/residue procedure. Copyright © 2007 John Wiley & Sons, Ltd.

Current–Voltage Characteristics of Long-Channel Nanobundle Thin-Film Transistors: A “Bottom-Up” Perspective

By generalizing the classical linear response theory of stick percolation to nonlinear regime, we find that the drain current of a Nanobundle Thin Film Transistor (NB-TFT) is described under a rather general set of conditions by a universal scaling formula ID = A/LS g(LS/LC, rho_S * LS * LS) f(VG, VD), where A is a technology-specific constant, g is function of geometrical factors like stick length (LS), channel length (LC), and stick density (rho_S) and f is a function of drain (VD) and gate (VG) biasing conditions. This scaling formula implies that the measurement of full I-V characteristics of a single NB-TFT is sufficient to predict the performance characteristics of any other transistor with arbitrary geometrical parameters and biasing conditions.

Modeling the impact of light on the performance of polycrystalline thin-film transistors at the sub-threshold region

The impact of the light illumination on the drain current of polycrystalline silicon thin-film transistors (TFT) is studied in this work. The increase of the output current as a result of raised light intensity is modeled, based on measured experimental data for different Vds and Vgs values and transistor sizes W/L. The proposed model has been verified against the measurements and the simulated output characteristics give a good approximation in the sub-threshold region.

Hot-carrier degradation analysis based on ring oscillators

This paper presents a new test circuit for hot-carrier degradation analysis based on a ring oscillator. The devices and the test circuit were fabricated using Philips’ 0.35 μm CMOS technology. For single device, AC and DC hot-carrier-induced degradation are the same if the effective stress time is carefully taken into account. For circuit level degradation, the frequency of the ring oscillator, on logarithmic scale degrades at the same slope as the saturation drain current of nMOS transistor degrades, while pMOS transistor degradation is much smaller than nMOSFET degradation and can be ignored. For universal applications, the circuit degradation can be expressed by MOSFETs I dsat degradation with NSF (nMOSFET degradation speed factor) and PSF (pMOSFET degradation speed factor). Formulae for NSF and PSF calculations are derived. Simulations with Philips PSTAR circuit simulator were also performed, which well agree with the experiment results.

Gate oxide induced switch-on undershoot current observed in thin-film transistors

The transient drain current of the single-grain silicon thin-film transistor with gate oxide deposited by electron cyclotron resonance plasma-enhanced chemical vapor deposition has been measured by applying a square signal on the gate and a constant low voltage between source and drain. Switch-on undershoot current has been observed, which can be attributed to the motion of space charge in gate oxide. Assuming there are some mobile ions in the gate oxide, we find the drift kinetics of the ions is quite similar to the mobile protons in SiO2, as reported in the literature.

A statistical methodology for the design of high-performance CMOS current-steering digital-to-analog converters

With the shrinking of device sizes, random device variations become a key factor limiting the performances of high-resolution complementary metal-oxide-semiconductor (CMOS) current-steering digital-to-analog converters (DACs). In this paper, we present a novel design methodology based on statistical modeling of MOS transistor drain current that allows designers to explore different DAC architectures and to study the effects of technological variations on system performance without using time-consuming Monte Carlo simulations. This technique requires as a first step the estimation of the mean value and the autocorrelation function of a single stochastic process. This stochastic process models the device drain current and summarizes all the random sources associated with the process/device variations since the current represents the effect of all of them. Subsequently, on the basis of such an approach, a behavioral model of current-steering DACs has been developed. Finally, the statistical simulation of static performances such as differential nonlinearity and integral nonlinearity has been carried out for different DAC architectures based on the behavioral model previously derived.

Reduction of source/drain series resistance and its impact on device performance for PMOS transistors with raised Si/sub 1-x/Gex source/drain

P-channel MOS transistors with raised Si/sub 1-x/Ge/sub x/ and Si source/drain (S/D) structure selectively grown by ultra high vacuum chemical vapor deposition (UHVCVD) were fabricated for the first time. The impact of Si/sub 1-x/Ge/sub x/ and Si epitaxial S/D layers on S/D series resistance and drain current of p-channel transistors were studied. Our results show that devices with the raised Si/sub 1-x/Ge/sub x/ S/D layer display only half the value of the specific contact resistivity and S/D series resistance (R/sub SD/), compared with those with a Si raised S/D layer. The improvement is even more dramatic when comparing with conventional devices without any raised S/D layer, i.e., R/sub SD/ of devices with Si/sub 1-x/Ge/sub x/ raised S/D is only about one fourth that of conventional devices. Moreover, the raised SiGe S/D structure produces a 29% improvement in transconductance (g/sub m/) at an effective channel length of 0.16 /spl mu/m. These performance improvements, together with several inherent advantages, such as self-aligned selective epitaxial growth (SEG) and the resultant T-shaped gate structure, make the new device with raised Si/sub 1-x/Ge/sub x/ S/D structure very attractive for future sub-0.1 /spl mu/m p-channel MOS transistors.

New simultaneous switching noise analysis and modeling for high-speed and high-density CMOS IC package design

A new simple but accurate simultaneous-switching-noise (SSN) model for complementary metal-oxide-semiconductor (CMOS) integrated circuit (IC) package design was developed. Since the model is based on the sub-micron metal-oxide-semiconductor (MOS) device model, it can predict the SSN for today's sub-micron-based very large scale integration (VLSI) circuits. In order to derive the SSN model, the ground path current is determined by taking into account all the circuit components such as the transistor resistance, lead inductance, load capacitance, and oscillation frequency of the noise signal. Since the current slew rate is not constant during the device switching, a rigorous analysis to determine the current slew rate was performed. Then a new simple but accurate closed-form SSN model was developed by accurately determining current slew rate for SSN with the alpha-power-law of a sub-micron transistor drain current. The derived SSN model implicitly includes all the critical circuit performance and package parameters. The model is verified with the general-purpose circuit simulator, HSPICE. The model shows an excellent agreement with simulation even in the worst case (i.e., within a 10% margin of error but normally within a 5% margin of error). A package design methodology is presented by using the developed model.

Dimension scaling of low frequency noise in the drain current of polycrystalline silicon thin-film transistors

Experimental results of low frequency noise in polycrystalline silicon thin-film transistors (polysilicon TFTs) with varying gate dimensions (constant gate width W and varying gate length L) are presented. The power spectral density of the drain current fluctuations SI was found to depend linearly on the inverse of the effective gate area Ag,eff which is related to the gate area W×L and the number of grains present within the transistor channel. This result implies localization of the low frequency noise sources on the gate oxide-polysilicon interface and on the grain boundaries. The 1/Ag,eff scaling law must be taken into account for correct estimation of trap densities in polysilicon TFTs.

300-kilo-Gate Sea-of-Gate Type Gate Arrays Fabricated Using 0.25-µm-Gate Ultra-Thin-Film Fully-Depleted Complementary Metal-Oxide-Semiconductor Separation by IMplanted OXygen (CMOS/SIMOX) Technology with Tungsten-Covered Source and Drain

A 120-kilo-gate (KG) fully functional gate-array LSI consisting of basic cells with a single-contact layout (single-contact cells) is fabricated on 300-KG sea-of-gate (SOG) type gate arrays using 0.25-µm ultra-thin-film fully-depleted (FD) complementary metal-oxide-semiconductor separation by implanted oxygen (CMOS/SIMOX) technology with selective W chemical vapor deposition (CVD). This paper shows that the performance of circuits made with single-contact cells can be as high as that with multi-contact cells, when the source/drain sheet resistance is below 5 Ω/sq. It also shows that selective W-CVD with the hydrogenation-and-hydrogen-termination (HHT) treatment can provide this sheet resistance even in ultra-thin-film silicon-on-insulator (SOI) substrates with a 50-nm-thick silicon layer. Single-contact cells built with selective W-CVD were applied to metal-oxide-semiconductor field effect transistors (MOSFETs), 2-input NAND circuits, and gate-array LSIs. Consequently, these cells did not degrade the drain current of transistors, or raise the gate delay time of the circuits. Single-contact cells built with W did not lower the yield of LSIs up to 120 KG compared to LSIs made with multi-contact cells without W. Furthermore, the 120-KG LSI consisting of single contact cells with W had no decrease in speed, compared to one with multi-contact cells. These results indicate that the selective W-CVD is a promising technology to increase the packing density of LSIs made with ultra-thin-film FD CMOS/SOI.

Capacitance and drain current deep level transient spectroscopy measurements on molecular beam epitaxy grown GaAs/ln0·25Ga0·75As/Al0·3Ga0·7As high electron mobility transistors

Modulation doped GaAs/In0·25Ga0·75As/Al0·3Ga0·7As high electron mobility transistor structures were grown using different molecular beam epitaxy growth temperatures and In0·25Ga0·75 As channel thicknesses. Drain current deep level transient spectroscopy (DLTS) and standard capacitance DLTS measurements were carried out on these devices using a Fourier transform technique. The results show that traps in the barrier as well as those in the buffer have an influence on the drain current of such transistors. In addition, a broadening of one of the DLTS peaks was observed for high channel thicknesses and is shown to be related to a high increase in dislocation concentration, as confirmed by cathodoluminescence measurements.MST/3323

Universality of mobility-gate field characteristics of electrons in the inversion charge layer and its application in MOSFET modeling

A mobility curve for electrons in a MOSFET inversion charge layer is determined from measured drain current of transistors produced by a wide range of MOS technologies. A comparison between this mobility curve and previously published results shows that a truly universal mobility curve does not exist and only local universal mobility curves can be expected, i.e. unique mobility curves which are valid over a finite range of MOS technologies and/or over a particular set of fabrication facilities. The curve's basic characteristic of being technology-independent over a wide range of process variation points out the potential of using such a local universal mobility curve as a powerful basis for developing predictive device modeling tools. This potential is demonstrated for an analytical MOSFET model and a two-dimensional device simulator where the mobility models have the general characteristics of experiment-based local universal mobility curves. >

New analytical expression for the drain current of short-channel MOS transistors in the triode region

Neglecting the effects of the source and drain electric fields on the depletion-layer charge, and consequently on the drain current, cannot be justified in short-channel MOS transistors. The existing geometrical approach for analysing this problem, known as a charge-sharing model, gives good agreement with experimental data only if an extremely complex expression for the drain current is used. In the letter the use of Gauss's law as a more general approach to analysis of the fringing field effect has been proposed. Using this approach, a simple expression for the drain current of short-channel MOS transistors, which shows excellent agreement with experimental data, has been derived.

Equilibrium Noise in Ion Selective Field Effect Transistors

Noise spectra of the drain current of ion selective field effect transistors in equilibrium were measured. The spectra differ from one type of ISFET to the other. The ionic activity in solution does not modify perceptibly the noise level for any of the various types of ISFET's. Computer assisted modeling is used to fit experimental data and to assign an equivalent electrical circuit to the electrochemical system. The overall response time of the system is shown to depend on the input capacitance of the electrometer.

Experimental and theoretical study of buried channel MOS structures

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