Drain Current Level Research Articles

Nonuniform threshold voltage profile in a-Si:H thin film transistor stressed under both gate and drain biases

In this paper we show that an a-Si:H thin film transistor (TFT) stressed with bias temperature stress (BTS) under both gate bias and drain bias produces a nonuniform threshold voltage profile which can be obtained from the quasi-Fermi potential profile and the threshold voltage (Vt)-shift data of BTS under the gate bias only. The transfer and output characteristics calculated with this nonuniform Vt-profile agreed well with the measured data, where the calculation was performed using both the gradual-channel approximation and independently the AIM Spice simulation with its level-15 a-Si TFT model. It is shown that local threshold voltage is high at the source and decreases toward the drain. Due to the nonuniform Vt-profile in the channel, the drain current level is higher in the forward direction, where the source and drain electrodes are the same between measurement and BTS, than in the reverse direction, where source and drain electrodes are interchanged. The forward and reverse I-V characteristics are somewhat similar to those of metal-oxide-semiconductor field-effect transistors with nonuniform channel doping.

Flexible high gain complementary inverter using n-ZnO and p-pentacene channels on polyethersulfone substrate

We report on the fabrication of complementary inverters that have ZnO and pentacene as n-type and p-type channels on a polyethersulfone substrate operating under 7V. Patterned Al and AlOx thin film were deposited at room temperature on the plastic as a common gate electrode and dielectric, respectively. After initial gate instability between ZnO channel and AlOx dielectric was controlled, our n-type thin-film transistors (TFTs) displayed quite a similar drain current level to that of p-type TFTs. Our flexible complementary device showed much high voltage gain of ∼100 even under a bent condition (56mm radius of curvature). Our complementary inverter also demonstrates a promising dynamic behavior of ∼20ms.

Characterization of Multistep Electron Charging and Discharging of a Silicon Quantum Dots Floating Gate by Applying Pulsed Gate Biases

Electron charging and discharging operations for a silicon quantum dots (Si-QDs) floating gate with discrete charged states were characterized in n-metal–oxide–semiconductor field-effect-transistors (MOSFETs) by applying single-pulsed gate biases Vg with pulse widths ranging from 10 ns to 100 ms. The drain current levels for charged states increase stepwise with Vg pulse width, which indicates multistep electron charging in the Si-QDs floating gate due to quantization energy and electron charging. The gate voltages required to minimize the time for charging and discharging the Si-QDs floating gate are limited by the leakage current through the control oxide, which partially compensates the charging or discharging current through the tunnel oxide in the high-gate-voltage region. The transient variation of the drain current at zero gate bias, after the application of pulsed gate biases for the dot floating gate to be charged, shows that a critical transition from an unstable charged state to a stable one occurs, depending on the pulse height or width. This suggests the redistribution of electrons in the floating gate during the metastable state, which involves a reduction in the effective charging energy and the resultant elimination of the Coulomb blockade.

Characterization of double gate TFTs fabricated in advanced SLS ELA polycrystalline silicon films

Double gate thin film transistors (TFTs) were fabricated in advanced excimer-laser annealed (ELA) polycrystalline silicon films, obtained by sequential lateral solidification (SLS), and their characteristics were investigated. The observed back gate effect on the I DS–V GS on–off curves indicated fully depleted active layers. The dependence of the device parameters for front gate operation on the back gate bias reflected the conduction behavior, with varying back channel contribution. While the double gate structure needs to be optimized for highest performance, the use of the back gate was determined both to result in effective threshold control, allowing for design flexibility, and also to make possible a reduced avalanche effect for similar drain current levels.

Correlation between static characteristics and deep levels in InAlAs/InGaAs/InP HEMT'S

It is well known that trapping effects can limit the output power performance of microwave field-effect transistors (FETs). This is particularly true for the wide band gap devices. In this paper, we present a detailed study of drain Current Deep Level Transient Spectroscopy CDLTS measurements performed on InAlAs/InGaAs/InP HEMT of two different samples. We demonstrate that a remarkable correlation exists between deep levels observed by CDLTS and the presence of parasitic effects such as kink and hysteresis effects.

Influence of the Dynamic Access Resistance in the<tex>$g_m$</tex>and<tex>$f_T$</tex>Linearity of AlGaN/GaN HEMTs

The decrease of transconductance g/sub m/ and current gain cutoff frequency f/sub T/ at high drain current levels in AlGaN/GaN high-electron mobility transistors (HEMTs) severely limits the linearity and power performance of these devices at high frequencies. In this paper, the increase of the differential source access resistance r/sub s/, with drain current is shown to play an important role in the fall of g/sub m/ and f/sub T/. The increase of r/sub s/ occurs due to the quasi-saturation of the electron velocity in the source region of the channel at electric fields higher than 10 kV/cm. This has been confirmed by both experimental measurements and two-dimensional drift-diffusion simulations. Through simulations, we have identified HEMT structures with source implanted regions (or n/sup ++/ cap layers) as good candidates in order to increase the linearity of the g/sub m/ and f/sub T/ versus current profile.

Silicon nanowires as enhancement-mode Schottky barrier field-effect transistors

Silicon nanowire field-effect transistors (SiNWFETs) have been fabricated with ahighly simplified integration scheme to function as Schottky barrier transistorswith excellent enhancement-mode characteristics and a high on/off current ratio∼107. SiNWFETs show significant improvement in the thermal emission leakage(∼6 × 10−13 A µm−1) compared to reference FETs with a larger channel width(∼7 × 10−10 A µm−1). The drain current level depends substantially on the contact metal work functionas determined by examining devices with different source/drain contacts of Ti(≈4.33 eV)and Cr (≈4.50 eV). The different conduction mechanisms for accumulation- and inversion-mode operationare discussed and compared with two-dimensional numerical simulation results.

Effect of 60 Co gamma‐irradiation on two‐dimensional electron gas transport and device characteristics of AlGaN/GaN HEMTs

The effect of 60Co gamma-irradiation on Al0.33Ga0.67N/GaN high-electron-mobility transistors (HEMTs) has been investigated using DC and geometrical magnetoresistance measurements. The devices studied were of similar epitaxial structure, yet differed in the doping levels of the Al0.33Ga0.67N barrier layer: (A) nominally undoped and (B) Si-doped with SiNx passivation. Exposure to cumulative gamma-ray doses up to 20 Mrad(Si) is shown to induce significant changes in drain-current level, threshold voltage and gate leakage current level. Analysis of magnetoresistance characteristics measured at 80 K indicated that irradiation induced an increase in two-dimensional electron-gas (2DEG) density, which leads to negative threshold voltage shifts observable in the drain current versus gate voltage characteristics, attributable to the introduction of defect centers in the Al0.33Ga0.67N layer and/or at the gate-AlGaN interface. The 2DEG mobility-concentration profiles are shown to remain approximately unchanged for doses up to 20 Mrad(Si). Device failure, evidenced as loss of gate control over the channel and/or excessive gate leakage, occurred after exposure to 30 Mrad(Si) for device A, whereas sample B failed after 20 Mrad(Si) total dose due to failure of half of the gate contact. Degradation of gate and source/drain contacts characteristics with total dose appears to limit the tolerance of the studied HEMTs to 60Co gamma-irradiation. (© 2005 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

Drain Current DLTS of AlGaN–GaN MIS-HEMTs

The transient behavior of AlGaN-GaN MIS-HEMTs were studied by drain current deep level transient spectroscopy. Two electron traps were observed, one of which had similar activation energy to that of defect that was commonly observed in epitaxial GaN. We compared the results with those of AlGaN-GaN HEMTs. The hole-trap-like positive peaks in the DLTS, which were observed in the HEMTs, were not observed in the MIS-HEMTs. It has been pointed out that the positive peaks did not originate from change in hole trap population in the channel but reflected the change in the electron population in the surface states of the HEMT access regions. The gate insulator was effective to suppress not only the gate leakage current but also the surface-state-related signals.

Substrate Bias Amplification of a SiC Junction Field Effect Transistor with a Catalytic Gate Electrode

The drain current-voltage (I-d-V-D) characteristics of a chemical gas sensor based on a catalytic metal insulator silicon carbide field effect transistor (SiC-FET) were measured in H-2 or O-2 ambient while applying negative substrate bias, V-sub, at temperatures up to 600degreesC. An increase in the negative V-sub gives rise to an increase of the drain voltage at a given drain current level, which can be used to adjust the device baseline. In addition, we found that the difference in drain voltage between H-2 and O-2 ambient at a given drain current level (the gas response to H-2) increases for an increased negative substrate bias. By modifying an equation for the drain current in a SIT (static induction transistor), the influence of substrate bias on the amplification factors, mu and eta, was estimated using the temperature dependence of the I-d-V-D characteristics. From this, the effect of substrate bias on the gas response to hydrogen was calculated. It was clarified that the increase in the gas response caused by the negative substrate bias is due to a substrate bias dependence of the amplification factor of the short channel device.

Fabrication and Characterization of Gate-Connected 1T2C-Type Ferroelectric Memory with Paired Bi4 − xLaxTi3O12 Capacitors

A gate-connected 1T2C-type ferroelectric memory, in which the bottom electrodes of paired ferroelectric capacitors are connected to the gate electrode of an underlying FET (field effect transistor) on the field oxide region, was fabricated using a Bi4 − xLaxTi3O12 (BLT) film and its electrical properties were characterized. The ID-VG (drain current-gate voltage) characteristics of a FET combined with a single ferroelectric capacitor showed that the paired capacitors had almost the same ferroelectric property. It was found in the readout operation that there existed an optimum voltage to maximize the drain current on/off ratio between datum ‘1’ and datum ‘0,’ and that the maximum ratio was as large as 6 × 104. It was also found that the drain current level remained constant, even if the readout operation was repeatedly conducted. It was concluded from these results that the 1T2C-type memory was successfully fabricated using the proposed process and operated properly.

A CAD methodology for optimizing transistor current and sizing in analog CMOS design

A computer-aided design (CAD) methodology for optimizing MOS transistor current and sizing is presented where drain current ID, inversion level (represented by inversion coefficient IC), and channel length L are selected as three independent degrees of design freedom resulting in an optimized selection of channel width for layout. At a given drain current I/sub D/ in saturation, a selected MOS inversion coefficient IC and channel length L define a point on an operating plane illustrating dramatic tradeoffs in circuit performance. Operation in the region of low inversion coefficient IC and long channel length L results in optimal DC gain and matching compared to the region of high inversion coefficient IC and short channel length L where bandwidth is optimal. A design methodology is presented here to enable optimum design choices throughout the continuum of inversion level IC (weak, moderate, or strong inversion) and available channel length L. The methodology is implemented in a prototype CAD system where a graphical view permits the designer to explore optimum tradeoffs against preset goals for circuit transconductance g/sub m/, output conductance g/sub ds/, drain-source saturation voltage, gain, bandwidth, white and flicker noise, and DC matching for a 0.5-/spl mu/m CMOS process. The design methodology can be readily extended to deeper submicron MOS processes through linkage to the EKV or BSIM3 MOS models or custom model equations.

The statistics of NBTI-induced V/sub T/ and β mismatch shifts in pMOSFETs

Negative bias temperature instability (NBTI) is a pFET degradation mechanism that can result in threshold voltage shifts up to 100 mV or more, even in very thin oxide devices. Since analog circuits that utilize matched pairs of devices, such as current mirrors and differential pairs, generally depend on V/sub T/ matching considerably better than this, NBTI-induced V/sub T/ mismatch shift may represent a serious reliability concern for CMOS analog applications. Furthermore, induced /spl beta/ mismatch shift (affecting drain current level at a fixed gate overdrive voltage) may also impact drain current and transconductance mismatch. In this paper, experimental results of the statistics and scaling properties of NBTI-induced V/sub T/ and /spl beta/ mismatch shifts in saturation, and models describing these results, are presented.

Electroluminescence and other diagnostic techniques for the study of hot-electron effects in compound semiconductor devices

Hot electron in III–V FETs can be indirectly monitored by measuring the current coming out from the gate when the device is biased at high electric fields. This negative current is due to the collection of holes generated by impact ionization in the gate-to drain region. Electroluminescence represents a powerful tool in order to characterize not only hot electrons but also material properties. By using spatially resolved emission microscopy it is possible to show that the light due to cold electron/hole recombination is emitted between the gate and the source (low electric field region), while the contribution due to hot electrons is emitted between the gate and the drain (high electric field region). Deep-traps created in the device by hot carriers can be analysed by means of drain current deep level transient spectroscopy and by transconductance frequency dispersion. Cathodoluminescence, optical beam induced current, X-ray spectroscopy, electron energy loss spectroscopy in combination with a transmission electron microscopy are powerful tools in order to identify and localize surface modification following hot-electron stress tests.

Evidence of interface trap creation by hot-electrons in AlGaAs/GaAs high electron mobility transistors

We report on the hot-electrons induced degradation in AlGaAs/GaAs high electron mobility transistors (HEMTs), consisting of a decrease in the drain current and an increase in the parasitic drain resistance. The amount of the degradation is proportional to the impact-ionization rate which is related to the electron energy. Transconductance dispersion measurements and drain current deep level transient spectroscopy (DLTS) have been used to identify interface traps which are located at the AlGaAs/GaAs interface in the gate-drain access region and are the causes of the observed degradation.

Modelling of the quasisaturation behaviour in the high-voltage MOSFET with vertical trench gate

The quasisaturation behaviour in the high voltage MOSFET structure with a vertical trench gate (UMOS) is studied and demonstrated using 2D numerical simulation techniques. The results show that the quasisaturation effect is mainly due to the conduction area and conductance of the drift region becoming the main constraint at high gate voltage and drain current levels. A simple analytical expression for the quasisaturation current using a simple resistive model is derived and verified based on the simulation results. The effect that the geometry of the trench has on the quasisaturation behaviour is studied, and it is found that increasing the depth and width of the trench improves the quasisaturation operation.

Capacitance and drain current deep level transient spectroscopy measurements on molecular beam epitaxy grown GaAs/ln0·25Ga0·75As/Al0·3Ga0·7As high electron mobility transistors

Modulation doped GaAs/In0·25Ga0·75As/Al0·3Ga0·7As high electron mobility transistor structures were grown using different molecular beam epitaxy growth temperatures and In0·25Ga0·75 As channel thicknesses. Drain current deep level transient spectroscopy (DLTS) and standard capacitance DLTS measurements were carried out on these devices using a Fourier transform technique. The results show that traps in the barrier as well as those in the buffer have an influence on the drain current of such transistors. In addition, a broadening of one of the DLTS peaks was observed for high channel thicknesses and is shown to be related to a high increase in dislocation concentration, as confirmed by cathodoluminescence measurements.MST/3323

Examination of oxide damage during high-current stress of n-MOS transistors

Damage to n-channel MOSFETs under different levels of drain current stress is compared. It is shown that the post-stress I/sub d/-V/sub gs/ characteristics show distinctly different behavior for different stresses. These differences are interpreted in terms of the location of the stress damage along the Si-SiO/sub 2/ interface. It is shown that damage from low drain current stress occurs at the Si-SiO/sub 2/ interface just inside the drain junction, under strong gate control. Damage from high drain current stress occurs at the Si-SiO/sub 2/ interface deeper inside the drain junction region, under weak gate control. The damage localization interpretation is supported by simulations and by localized Fowler-Nordheim injection experiments. It is further shown that at intermediate levels of drain current injection, the damage occurs at the Si-SiO/sub 2/ interface in both drain regions. The differences are explained in terms of the bipolar action at high drain current levels, which forces the channel charge away from the Si-SiO/sub 2/ interface at the drain junction edge.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

High transconductance InGaAs/AlGaAs pseudomorphic modulation-doped field-effect transistors

Pseudomorphic In <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.15</inf> Ga <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.85</inf> As/Al <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.15</inf> Ga <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.85</inf> As modulation-doped field effect transistors (MODFET's) exhibiting extremely good dc characteristics have been successfully fabricated, dc transconductance in these strained-layer structures of 270 mS/mm were measured for 1-µm gate, normally-on devices at 300 K. Maximum drain current levels are 290 mA/mm, with excellent pinch-off and saturation characteristics. The transconductance increased to 360 mS/mm at 77 K while no persistent photoconductivity or drain collapse was observed. Preliminary microwave results indicate a 300-K current gain cutoff frequency of about 20 GHz. These results are equivalent to the best GaAs/AlGaAs MODFET results and are due in part to the improved transport properties and carrier confinement in the InGaAs quantum well.

Annealing characteristics of ion-implanted p-channel MOS transistors

The annealing characteristics of 50-keV (2–3) × 1011/cm2 11B+-implanted p-channel MOS transistors were investigated from 300 to 900°C. Below 500°C, the number of activated atoms NII decreased rapidly with decreasing anneal temperature and the C-V characteristics showed gradual distortions. This was presumably due to surface states induced by the ion implantation. Above 500°C, NII increased only slightly with increasing anneal temperature and the slope of the C-V characteristics in the transition region was larger than that of the unimplanted sample. Corresponding to the above features, the gain term increased near 500°C to a value about 30% larger than that of the unimplanted sample, while the breakdown voltage decreased below 500°C. Equivalent noise voltage decreased abruptly from 500 to 600°C. However, at lower drain current levels, the generation-recombination noise spectrum did not disappear, even after a 900°C anneal. In addition, reverse-annealing-like phenomena were observed in the equivalent noise voltage between 350 and 450°C. The results of surface recombination velocity measurements were consistent qualitatively with the results of equivalent noise-voltage measurements. Furthermore, device stability was confirmed by positive and negative bias-temperature treatments (250°C, 1 h, Eox = ± 6.7 × 105 V/cm) for devices annealed above 450°C.