Annealing characteristics of ion-implanted p-channel MOS transistors

Abstract

The annealing characteristics of 50-keV (2–3) × 1011/cm2 11B+-implanted p-channel MOS transistors were investigated from 300 to 900°C. Below 500°C, the number of activated atoms NII decreased rapidly with decreasing anneal temperature and the C-V characteristics showed gradual distortions. This was presumably due to surface states induced by the ion implantation. Above 500°C, NII increased only slightly with increasing anneal temperature and the slope of the C-V characteristics in the transition region was larger than that of the unimplanted sample. Corresponding to the above features, the gain term increased near 500°C to a value about 30% larger than that of the unimplanted sample, while the breakdown voltage decreased below 500°C. Equivalent noise voltage decreased abruptly from 500 to 600°C. However, at lower drain current levels, the generation-recombination noise spectrum did not disappear, even after a 900°C anneal. In addition, reverse-annealing-like phenomena were observed in the equivalent noise voltage between 350 and 450°C. The results of surface recombination velocity measurements were consistent qualitatively with the results of equivalent noise-voltage measurements. Furthermore, device stability was confirmed by positive and negative bias-temperature treatments (250°C, 1 h, Eox = ± 6.7 × 105 V/cm) for devices annealed above 450°C.