Double SOI Research Articles

Tip-Tilt-Decoupled Vertical Comb-Drive Micromirror Based on D-SOI Wafer and Interlayer TSV

Abstract Mechanical cross-axis coupling in biaxial scanning increases calibration workload and affects performance of tip-tilt (TT) micromirror. The integration of gimbal and inner-axis vertical comb-drive (VCD) actuator is a viable design for TT-decoupled micromirror. The key to developing such structure is guaranteeing integrated inner-axis VCD actuator insulated from the gimbal and electrically connected to the substrate while minimizing fabrication difficulty. For this purpose, this paper introduces double-silicon-on-insulator (D-SOI) wafer that has two mutually-insulated device layers into the development of TT-decoupled VCD micromirror. For both tip and tilt scanning modes, two vertical comb (VC) sets in each VCD actuator are arranged on different device layers of the D-SOI wafer. Gimbal, reflective mirror and springs are fabricated on the identical device layer of the D-SOI wafer, forming an integrated structure together with inner-axis VCD actuator. Besides, polysilicon-based interlayer through-silicon-vias (TSVs) and surface metal redistribution layers (RDLs) are employed to electrically connect all the driving signals to the wiring substrate. The D-SOI wafer is bonded to the wiring substrate using the thermocompression bonding processing before removing D-SOI handle layer and structure release. Based on the proposed structure and micromachining process, this paper fabricates 3×3 micromirror array (MMA), in which each pixel is 951×1096 μm2 in footprint and has fill factor of 50 %. Testing results of fabricated MMA exhibit a quasi-static mechanical tilt/tip angle of 1.266/1.436 ° at 35/35 volt, and RMS reflective mirror roughness of 5.323 nm.

Low-frequency noise in the Double SOI (DSOI) MOSFETs with back-gate control

In this paper, the impact of the back-gate voltage (Vb ) on the low-frequency (1/f) noise is evaluated for the 180 nm double silicon-on-insulator (DSOI) NMOS, fabricated with various thicknesses of first buried oxide (BOX1) layer (145/50 nm). Both positive and negative Vb increased the measured normalized drain current power spectral density (PSD) for more than ten-fold in DSOI standard devices with 145 nm BOX1, while the normalized PSD decreases with Vb going up in devices with 50 nm BOX1. By comparing with CNF+CMF model, interface trap density and the Coulomb scattering coefficient are extracted with the back-gate voltage applied. The interface trap density increases in standard devices for both positive and negative Vb , but decreases with increasing back-gate biasing from -10 V to 10 V in devices with 50 nm BOX1. The interface trap density shows a similar back-gate coupling effect with threshold voltage under the influence of different thickness of BOX1. The CNF and CMF noise variation under back-gate voltage can be explained by the significant fluctuation in drain current.

Total Ionizing Dose Effect and Radiation Hardness Analysis on Low-Leakage ESD Devices Fabricated on Double SOI Technology

Total Ionizing Dose Effect and Radiation Hardness Analysis on Low-Leakage ESD Devices Fabricated on Double SOI Technology

Novel dynamic back-gate control technology for performance improvement in ultrathin double SOI LDMOS

Novel dynamic back-gate control technology for performance improvement in ultrathin double SOI LDMOS

Assessment of 180 nm double SOI technology for analog front-end design with back-gate voltage

This paper provides an assessment of the electrical and noise performance in the 180 nm double silicon-on-insulator (DSOI) technology, which shows advantages for analog front-end radiation detectors. For the first time, the impact of the back-gate voltage on the electrical and noise performance of DSOI MOSFETs is investigated. The transconductance-to-current (gm /ID ) ratio and low-frequency (1/f) noise were measured as a function of the MOS device types (NMOS/PMOS), gate length, and bias condition of front- and back-gates. Experimental results show that positive back-gate voltage deteriorates the gm /ID ratio of the MOSFETs in weak inversion region. The DSOI NMOS devices overwhelm the PMOS with better gm /ID and 1/f performance. The DSOI devices have a comparable 1/f noise with the 180 nm SOI counterparts. With negative back-gate voltage applied, the low frequency noise performance of NMOS is improved. This assessment of DSOI technology gives a guideline for the readout circuit design in detector front-end systems.

Robustness-Improved ESD Protection Devices With Low Leakage Using Middle Silicon Layer in Double SOI Technology

Robustness-Improved ESD Protection Devices With Low Leakage Using Middle Silicon Layer in Double SOI Technology

Comparison of Total Ionizing Dose Effects between Double and Conventional SOI Devices

Comparison of Total Ionizing Dose Effects between Double and Conventional SOI Devices

Numerical Investigation of Transient Breakdown Voltage Enhancement in SOI LDMOS by Using a Step P-Type Doping Buried Layer

In this paper, the transient breakdown voltage (TrBV) of a silicon-on-insulator (SOI) laterally diffused metal-oxide-semiconductor (LDMOS) device was increased by introducing a step P-type doping buried layer (SPBL) below the buried oxide (BOX). Device simulation software MEDICI 0.13.2 was used to investigate the electrical characteristics of the new devices. When the device was turned off, the SPBL could enhance the reduced surface field (RESURF) effect and modulate the lateral electric field in the drift region to ensure that the surface electric field was evenly distributed, thus increasing the lateral breakdown voltage (BVlat). The enhancement of the RESURF effect while maintaining a high doping concentration in the drift region (Nd) in the SPBL SOI LDMOS resulted in a reduction in the substrate doping concentration (Psub) and an expansion of the substrate depletion layer. Therefore, the SPBL both improved the vertical breakdown voltage (BVver) and suppressed an increase in the specific on-resistance (Ron,sp). The results of simulations showed a 14.46% higher TrBV and a 46.25% lower Ron,sp for the SPBL SOI LDMOS compared to those of the SOI LDMOS. As the SPBL optimized the vertical electric field at the drain, the turn-off non-breakdown time (Tnonbv) of the SPBL SOI LDMOS was 65.64% longer than that of the SOI LDMOS. The SPBL SOI LDMOS also demonstrated that TrBV was 10% higher, Ron,sp was 37.74% lower, and Tnonbv was 10% longer than those of the double RESURF SOI LDMOS.

The Study of Hot Carrier Effects on Double SOI NMOSFETs

Hot carrier injection tests were performed on 0.18 μm Double SOI H-gate NMOSFETs in the body-grounded and floating-body states under two different bias conditions: Vg@Ib,peak and Vg = Vd. The experimental results show that, in the body-grounded state, both Vthlin and Vthsat degrade more significantly under Vg = Vd condition than Vg@Ib,peak, and the degradation of Vthlin is greater than that of Vthsat; in the floating-body state, the degradation trend of Vthsat is consistent with the former case, however, due to the existence of the history effect caused by the floating body effect, the Vthlin reduce first and then increase with the stress time. Therefore, when predicting the lifetime of the device, the worst-case condition and the measured parameters used to characterize device degradation should be selected properly.

Back gate impact on SEU characterization of a Double SOI 4k-bit SRAM

In this paper, heavy-ion single-event effects studies are investigated on a 0.2 μm Double silicon-on-insulator (DSOI) 4k bit Static Random Access Memory (SRAM). The back gate bias is used to adjust the single event upset (SEU) rate of the SRAM circuit. Experimental results show that applying a -5 V bias to the back gate of nMOSFETs can reduce the SEU cross section by 31 % ~ 62 %, and the SEU rate by 61 %. While applying to the back gate of both nMOSFETs and pMOSFETs a 5 V bias can increase the SEU cross section by 43 % ~ 298 %, and the SEU rate by 3 orders of magnitude. The SEU rate is calculated using OMERE software under the GEO orbit with a 3 mm aluminum shielding condition. To further analyze the cause of this phenomenon, TCAD simulation and DSOI MOSFETs test were introduced in this paper. Results show that applying a negative bias to the back gate of nMOSFETs will reduce the single particle transient (SET) and increase the threshold voltage of nMOSFETs, which makes the SRAM cell more tolerant to SEU; while applying a positive bias to the back gate of pMOSFETs will decrease the drive current of pMOSFETs, which makes the SRAM cell more sensitive to SEU.

X-ray radiation damage effects on double-SOI pixel detectors for the future astronomical satellite FORCE

We have been developing the monolithic active pixel detector XRPIX onboard the future x-ray astronomical satellite FORCE. XRPIX is composed of complementary metal-oxide-semiconductor pixel circuits, SiO2 insulator, and Si sensor by utilizing the silicon-on-insulator (SOI) technology. When the semiconductor detector is operated in orbit, it suffers from radiation damage due to x-rays emitted from celestial objects as well as cosmic rays. From previous studies, positive charges trapped in the SiO2 insulator are known to cause degradation of the detector performance. To improve the radiation hardness, we developed XRPIX equipped with a double-SOI (D-SOI) structure, introducing an additional silicon layer in the SiO2 insulator. This structure is aimed at compensating for the effect of the trapped positive charges. Although the radiation hardness of the D-SOI detectors to cosmic rays has been evaluated, the radiation effect due to x-ray irradiation has not been evaluated. Thus, we then conduct an x-ray irradiation experiment using an x-ray generator with a total dose of 10 krad at the SiO2 insulator, equivalent to 7 years in orbit. As a result of this experiment, the energy resolution in full-width half maximum for the 5.9 keV x-ray degrades by 17.8 % ± 2.8 % and the dark current increases by 89 % ± 13 % . We also investigate the physical mechanism of the increase in the dark current due to x-ray irradiation using technology computer-aided design simulation. It is found that the increase in the dark current can be explained by the increase in the interface state density at the Si / SiO2 interface.

Investigation of Negative Bias Effect on Radiation Hardening for Double SOI Technology

Double silicon-on-insulator (DSOI) technology featuring two buried oxide layers under silicon film has drawn excessive attention to space applications by modulating the electric field in back channel. This article studied the impact of the total ionizing dose (TID) effect on the n-channel metal oxide semiconductor field effect transistors (nMOSFETs) based on DSOI materials. Radiation-induced degradation in performance only appeared in the metal oxide semiconductor field effect transistor (MOSFET) with <inline-formula> <tex-math notation="LaTeX">$W/L = 0.15~\mu \text{m}$ </tex-math></inline-formula>/10 <inline-formula> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> after 1.5 Mrad(Si) irradiation and recovered with negative <inline-formula> <tex-math notation="LaTeX">$V_{\mathrm {bg}}$ </tex-math></inline-formula> applied. However, due to the weak coupling effect between the front and back gates, the threshold voltage (<inline-formula> <tex-math notation="LaTeX">$V_{\mathrm {th}}$ </tex-math></inline-formula>) of nMOSFET with <inline-formula> <tex-math notation="LaTeX">$W/L = 10~\mu \text{m}$ </tex-math></inline-formula>/10 <inline-formula> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> and <inline-formula> <tex-math notation="LaTeX">$10~\mu \text{m}/0.13~\mu \text{m}$ </tex-math></inline-formula> declined 0.06 V compared with devices before irradiation when <inline-formula> <tex-math notation="LaTeX">$V_{\mathrm {bg}}$ </tex-math></inline-formula> is set to 0 V. The TCAD simulation and testing results reveal that the electric field introduced by negative back-gate bias could effectively mitigate the TID-induced performance degradation in DSOI nMOSFETs. The investigation will facilitate the application of DSOI technology for high-radiation-dose conditions.

Total Ionizing Dose Radiation Effects Hardening Using Back-Gate Bias in Double-SOI Structure

To mitigate the total ionizing dose (TID) radiation impact, a new structure named double-silicon-on-insulator (DSOI) is introduced in this article. This new structure exhibits potential benefits of reducing the radiation-induced degradation effectively and independently, thanks to the additional electrode, which can be used to control the internal electrical field of the device. With this structure, the TID response and TID mitigation strategy using back-bias are discussed in DSOI nMOSFETs. Then, a 3-D TCAD simulation model is proposed to analyze the radiation-induced leakage path for each bias configuration. The impact of negative back-bias during irradiation on trapped charge distribution is given for both buried oxide layer and shallow trench isolation. At last, a 4k-bit static random access memory is used to verify the effectiveness of back-bias on TID-induced leakage current suppression at the circuit level. The experimental results show the possibility of using back-bias against TID threat.

Dependence of Temperature and Back-Gate Bias on Single-Event Upset Induced by Heavy Ion in 0.2-μm DSOI CMOS Technology

The dependence of temperature and back-gate bias on single-event upset (SEU) sensitivity is investigated based on a 0.2-<inline-formula> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> double silicon-on-insulator (DSOI) technology. At room temperature, an obvious decrease in SEU cross section with the negative back-gate bias is experimentally observed for a DSOI static random access memory (SRAM). The physical mechanism of single-event effect (SEE) is explained through technology computer-aided design (TCAD) simulations. TCAD simulations were also performed to explain the impact of back-gate bias on charge collection and full width at half maximum (FWHM) of the pulsewidth at various temperatures. Both charge collection and FWHM of the pulsewidth increase significantly with temperature rising from 240 to 400 K. It is demonstrated that the SEU threshold linear energy transfer (LET) for a DSOI 6T SRAM cell decreases with an increase in temperature. Compared with a fully depleted SOI (FDSOI) technology, the unique independent back-gate bias scheme for a DSOI SRAM cell exhibits higher tolerance to SEU. At 400 K, it is found that the SEU threshold LET (LET_th) for a DSOI 6T SRAM cell increases by 12.5&#x0025; with back-gate bias of nMOS reduced from 0 to &#x2212;15 V.

High spatial resolution monolithic pixel detector in SOI technology

This paper presents test-beam results of monolithic pixel detector prototypes fabricated in 200 nm Silicon-On-Insulator (SOI) CMOS technology studied in the context of high spatial resolution performance. The tested detectors were fabricated on a 500 μm thick high-resistivity Floating Zone type n (FZ-n) wafer and on a 300 μm Double SOI Czochralski type p (DSOI Cz-p) wafer. The pixel size is 30 μm×30 μm and two different front-end electronics architectures were tested, a source follower and a charge-sensitive preamplifier. The test-beam data analyses were focused mainly on determination of the spatial resolution and the hit detection efficiency. In this work different cluster formation and position reconstruction methods are studied. In particular, a generalization of the standard η-correction adapted for arbitrary cluster sizes, is introduced. The obtained results give in the best case a spatial resolution of about 1.5 μm for the FZ-n wafer and about 3.0 μm for the DSOI Cz-p wafer, both detectors showing detection efficiency above 99.5%.

Spectroscopic performance improvement of SOI pixel detector for X-ray astronomy by introducing Double-SOI structure

This paper reports the spectroscopic performance improvement of the silicon-on-insulator (SOI) pixel detector for X-ray astronomy, by introducing a double-SOI (D-SOI) structure. For applications in X-ray astronomical observatories, we have been developing a series of monolithic active pixel sensors, named as “XRPIXs,” based on SOI pixel technology. The D-SOI structure has an advantage that it can suppress a parasitic capacitance between the sensing node and the circuit layer, due to which the closed-loop gain cannot be increased in our conventional XRPIXs with a single-SOI (S-SOI) structure. Compared to the S-SOI XRPIX, the closed-loop gain is doubled in the D-SOI XRPIX. The readout noise is effectively lowered to 33% (16 e− (rms)), and the energy resolution at 6.4 keV is improved by a factor of 1.7 (290 eV in FWHM). The suppression of the parasitic capacitance is also quantitatively evaluated based on the results of capacitance extraction simulation from the layout. This evaluation provides design guidelines for further reduction of the readout noise.

Radiation damage effects on double-SOI pixel sensors for X-ray astronomy

The X-ray SOI pixel sensor onboard the FORCE satellite will be placed in the low earth orbit and will consequently suffer from the radiation effects mainly caused by geomagnetically trapped cosmic-ray protons. Based on previous studies on the effects of radiation on SOI pixel sensors, the positive charges trapped in the oxide layer significantly affect the performance of the sensor. To improve the radiation hardness of the SOI pixel sensors, we introduced a double-SOI (D-SOI) structure containing an additional middle Si layer in the oxide layer. The negative potential applied on the middle Si layer compensates for the radiation effects, due to the trapped positive charges. Although the radiation hardness of the D-SOI pixel sensors for applications in high-energy accelerators has been evaluated, radiation effects for astronomical application in the D-SOI sensors has not been evaluated thus far. To evaluate the radiation effects of the D-SOI sensor, we perform an irradiation experiment using a 6-MeV proton beam with a total dose of ∼5krad, corresponding to a few tens of years of in-orbit operation. This experiment indicates an improvement in the radiation hardness of the X-ray D-SOI devices. On using an irradiation of 5 krad on the D-SOI device, the energy resolution in the full-width half maximum for the 5.9-keV X-ray increases by 7±2%, and the chip output gain decreases by 0.35±0.09%. The physical mechanism of the gain degradation is also investigated; it is found that the gain degradation is caused by an increase in the parasitic capacitance due to the enlarged buried n-well.

Total ionization dose effects and compensation in a counting type double SOI pixel sensor

We are developing the monolithic pixel sensors based on a 0.2 μm fully-depleted Silicon-on-Insulator (SOI) technology. One of the major issues in the SOI device is the total ionization dose (TID) effects in high-radiation environment. We studied the TID effects on a fully functional counting type pixel sensor based on Double SOI process. The device was irradiated to different dose at different region, by an X-ray tube operated at 30 kV with copper target. The degradation of the SOI MOSFET characteristics and the pixel response have been studied. The SPICE simulations using the transistor model with TID dose were performed on the pixel amplifier-shaper-discriminator (ASD) circuit to understand the malfunction in circuit level. In double SOI sensor, the SOI2 layer could compensate the positive charge induced by TID in buried oxide (BOX) layer when negatively biased. Such a compensation effectiveness has been observed in a counting type pixel sensor CPIXTEG3b.

Variable-K double trenches SOI LDMOS with high-concentration P-pillar**Project supported by the Scientific Research Fund of Hunan Provincial Education Department, China (Grant No. 19K001).

A variable-K trenches silicon-on-insulator (SOI) lateral diffused metal–oxide–semiconductor field-effect transistor (MOSFET) with a double conductive channel is proposed based on the enhancement of low dielectric constant media to electric fields. The device features variable-K dielectric double trenches and a P-pillar between the trenches (VK DT-P LDMOS). The low-K dielectric layer on the surface increases electric field of it. Adding a variable-K material introduces a new electric field peak to the drift region, so as to optimize electric field inside the device. Introduction of the high-concentration vertical P-pillar between the two trenches effectively increases doping concentration of the drift region and maintains charge balance inside it. Thereby, breakdown voltage (BV) of the device is increased. The double conductive channels provide two current paths that significantly reduce specific on-resistance (Ron,sp). Simulation results demonstrate that a 17-μm-length device can achieve a BV of 554 V and a low on-resistance of 13.12 mΩ⋅cm2. The Ron,sp of VK DT-P LDMOS is reduced by 78.9% compared with the conventional structure.

Sub-pixel response of double-SOI pixel sensors for X-ray astronomy

We have been developing the X-ray silicon-on-insulator (SOI) pixel sensor called XRPIX for future astrophysical satellites. XRPIX is a monolithic active pixel sensor consisting of a high-resistivity Si sensor, thin SiO2 insulator, and CMOS pixel circuits that utilize SOI technology. Since XRPIX is capable of event-driven readouts, it can achieve high timing resolution greater than ∼10 μs, which enables low background observation by adopting the anti-coincidence technique. One of the major issues in the development of XRPIX is the electrical interference between the sensor layer and circuit layer, which causes nonuniform detection efficiency at the pixel boundaries. In order to reduce the interference, we introduce a Double-SOI (D-SOI) structure, in which a thin Si layer (middle Si) is added to the insulator layer of the SOI structure. In this structure, the middle Si layer works as an electrical shield to decouple the sensor layer and circuit layer. We measured the detector response of the XRPIX with D-SOI structure at KEK. We irradiated the X-ray beam collimated with 4 μmϕ pinhole, and scanned the device with 6 μm pitch, which is 1/6 of the pixel size. In this paper, we present the improvement in the uniformity of the detection efficiency in D-SOI sensors, and discuss the detailed X-ray response and its physical origins.