Double Patterning Process Research Articles

Understanding Growth Mechanism of Atomic Layer Deposition of Tisiox for Spacer in Double Patterning Process

The aggressive scaling down of patterning technology in semiconductor industry is challenging owing to the limitation of current extreme ultraviolet EUV lithography technique, thus applying self-aligned double patterning (SADP) is essential. In this regard, TiSiOx may be a promising spacer material for SADP, which is beneficial to tolerate high aspect ratio structure triggered by shrinkage in patterning size. However, atomic layer deposition (ALD) of quaternary materials is usually faced to unexpected growth characteristics leading to undesired film qualities, while precise control of thickness and film properties is vital to achieve SADP. This work provide understanding of how growth characteristics of ALD TiSiOx are deviated according to process temperature. At 100 °C, hygroscopic TiSiOx surface which is originated by the presence of Ti-O-Si bond is exposed to H2O by-product leading to enhanced growth rate of TiSiOx compared to ideal case. If the process temperature is increased to 200 °C, opposite behavior is observed since hygroscopic TiSiOx surface characteristic is no more dominant to growth rate of ALD TiSiOx due to dehydroxylation. Theses nonconventional growth characteristics dramatically influence on hydroxyl concentration in TiSiOx films resulting in different spacer qualities such as dry etch rate and elastic modulus. These correlative results suggest that the process conditions should be modulated to suppress hydroxyls incorporation into growing TiSiOx surface during ALD to obtain a high-quality TiSiOx thin films for SADP.

Self-Expansion Based Multi-Patterning for 2D Materials Fabrication beyond the Lithographical Limit.

Two-dimensional (2D) materials are promising successors for silicon transistor channels in ultimately scaled devices, necessitating significant research efforts to study their behavior at nanoscopic length scales. Unfortunately, current research has limited itself to direct patterning approaches, which limit the achievable resolution to the diffraction limit and introduce unwanted defects into the 2D material. The potential of multi-patterning to fabricate 2D materials features with unprecedented precision and low complexity at large scale is demonstrated here. By combining lithographic patterning of a mandrel and bottom-up self-expansion, this approach enables pattern resolution one order of magnitude below the lithographical resolution. In-depth characterization of the self-expansion double patterning (SEDP) process reveals the ability to manipulate the critical dimension with nanometer precision through a self-limiting and temperature-controlled oxidation process. These results indicate that the SEDP process can regain the quality and morphology of the 2D material, as shown by high-resolution microscopy and optical spectroscopy. This approach is shown to open up new avenues for research into high-performance, ultra-scaled 2D materials devices for future electronics.

Process window improvement for fin cut layer in self-aligned double-patterning process based on backscattered electron imaging

BackgroundThe self-aligned double-patterning (SADP) process is being used extensively to overcome the lithographic resolution limit in the manufacture of integrated circuits. One use case is fin definition in a fin field-effect transistor. Fin cut layers are applied to modify the fins to the requirements of the device designs.AimThe traditional secondary electron (SE) imaging exhibits a disadvantage in the process controlling the fin cut layers, and fin damage defects were observed. This work aims to improve the monitoring and controlling capabilities for the process quality of fin cut layers.ApproachA specially designed fin cut process flow and a backscattered electron (BSE) imaging technique are applied to check the process quality. The patterns formed through the fin cut etch and the fin structures are identified and measured simultaneously in one BSE image.ResultsBy measuring the edge-to-edge distance, pitch walking (PW) of fins, and overlay (OV), the root cause of the fin damage is revealed. The linear fitting model and third-order fitting model are applied to reduce the edge placement error (EPE). The edge distance protecting the “at risk” fin is enlarged from 5.6 to 11.6 nm. The range of the distance is reduced from 11.6 to 8.1 nm, and the improvement in standard deviation is about 33%.ConclusionsThis work shows the capability of the BSE imaging technique in the characterization of fin cut layers and the potential in process window improvement restricted to fin damage defects.

Bottom grating asymmetry-induced inaccuracy in diffraction-based overlay measurement

Background: Overlay (OV) is a very important indicator for characterizing the pattern position accuracy between two layers in an integrated circuit in the manufacturing industry. The self-aligned double-patterning (SADP) process, which is limited to the resolution of deep ultraviolet lithography, is being extensively used for the volume manufacturing of integrated circuits. However, compared to the planar process, the SADP process poses new challenges for OV control.Aim: We investigate the bottom grating asymmetry of a microdiffraction-based overlay (μDBO) target in the SADP process and its effect on OV measurement.Approach: The bottom grating of the OV metrology target is analyzed through scanning electron microscopy and transmission electron microscopy. The imbalance of the −1st- and +1st-order diffraction light intensities of the asymmetrical bottom OV target is characterized. Finally, the effects of light polarization and wavelength on the OV accuracy are simulated.Results: Asymmetric behavior of bottom OV grating is identified. OV dependency on the measurement-light polarization is determined. The simulation results indicate that wavelength and polarization affect the OV accuracy simultaneously.Conclusions: We studied the bottom grating asymmetry-induced inaccuracy in DBO measurement and can assist in understanding the mechanism of measurement light-interaction with the OV grating to enhance the DBO accuracy to a new level.

(Invited) Process Development of CMOS TFTs for Monolithic 3D-IC Applications

Three-dimensional integrated circuit (3D-IC) technology has been used for vertical integration of multi-chip or stacked process in three-dimensional space for the scaling trend of sub-1 nm technical node, in order to overcome the physical limits of electronics and materials in the semiconductor process. Among them, monolithic 3D-IC has many features that can solve the challenge of stacking 2D molds and connecting them in the third dimension. 3D-IC has many significant advantages, such as heterogeneous integration, a smaller footprint but more powerful features, lower costs, reduced power, and higher bandwidth.In this talk, process development of CMOS thin film transistor (TFT) for monolithic 3D-IC will be presented. The channel material of upper layer is the key concern for fabricating device stacked in 3-D space due to the process thermal budget. An amorphous indium gallium zinc oxide (a-IGZO) with activation temperature under 350 ℃ is regarded as the most promising transparent amorphous oxide semiconductor (TAOS) channel material for the advanced TFT device. However, the TAOS TFT is lack of p-channel device. Hence in this work, a top gate poly-Si p-channel TFT (pTFT) device was formed with tri-gate structure by using a self-aligned double patterning (SADP) process. Then, an a-IGZO n-channel TFT (nTFT) based on a bottom gate process were stacked with a monolithic architecture on the same wafer.At first, the process development and optimization of individual AOS nTFT and poly-Si pTFT were carried out. The device structure of AOS nTFT includes a 100 nm-thick TiN metal bottom-gate, 10 nm-thick HfO2 gate dielectric, and IGZO channel. On the other hand, a 100 nm-thick TiN metal top-gate, 10 nm-thick HfO2/ 1 nm-thick SiO2 gate stack, p-type JL poly-Si channel, and tri-gate structure were applied for the poly-Si pTFT. Results show that the on/off current ratio (Ion/Ioff) values of AOS nTFT and poly-Si pTFT are 7 and 6.8 orders, respectively. And the subthreshold swing (S.S.) values are135 and 128 mV/decade, respectively. The device performance of the individual n/p TFTs in this work is similar to that of state-of-the-art devices.Afterwards, hybrid CMOS inverter devices were fabricated and stacked with a monolithic 3D-IC architecture. The Ion/Ioff values of AOS nTFT and poly-Si pTFT are 7.1 and 6.3 orders, respectively. And the S.S. values are135 and 133 mV/decade, respectively. The device performance is quite similar to those of individual n/p TFT fabricated in our group before. Results indicate that the process integration of the AOS nTFT and poly-Si pTFT for monolithic IC is successful. The electrical characteristics of CMOS TFT inverter are pretty good. The voltage gain is ~ 25, the mid voltage is ~ 0.5 Vdd, and the high/low noise margins are large and approximately equal.In order to further improve the performance of nTFT, a novel tungsten (W) dopant was applied to replace gallium (Ga) for ASO film due to its lower price and higher oxygen bond dissociation energy. With higher oxygen bond dissociation energy, the oxygen vacancy can be well controlled and the device may achieve better electrical and reliability characteristics. It is found that the a-IWZO nTFT shows a ION/IOFF value of 7.8 order and a S.S. value of 109 mV/decade. Furthermore, the mobility of a- IWZO TFT is about 2 times higher than that of a-IGZO TFT. The a-IWZO TFT with tiny W dopant as the carrier suppressor can exhibit a smaller S.S. value, suggesting that the channel can be effectively controlled even with higher channel conductivity.To further improve the performance of pTFT, a polycrystalline germanium (poly-Ge) junctionless (JL) TFT is studied. The implantation and activation processes are not required for poly-Ge JL device because the vacancy and interstitial in poly-Ge film can act as acceptors, which naturally turn the film into p-type. However, Ge with poor thermal stability is very sensitive to process temperature. The Ge sub-oxides at Ge surface have lower bandgap, more oxide traps, and interface states, and they may diffuse into gate dielectric after thermal process, resulting in degradation of gate dielectric. The desorption and diffusion of GeOx can be suppressed by nitridation process on interfacial layer (IL) at high-k/Ge. Therefore, in this work, poly-Ge JL pTFT devices with various ILs including GeO2, GeON, O2 plasma-treated HfN, and O2 plasma-treated Al2O3 HfO2 are investigated and compared. The optimal IL for poly-Ge pTFT could be expected. Then, a CMOS device by integrating AOS nTFT and poly-Ge pTFT with a monolithic architecture will be performed as well.

Quasi-bound states in the continuum for deep subwavelength structural information retrieval for DUV nano-optical polarizers.

We demonstrate the retrieval of deep subwavelength structural information in nano-optical polarizers by scatterometry of quasi-bound states in the continuum (quasi-BICs). To this end, we investigate titanium dioxide wire grid polarizers for application wavelengths in the deep ultraviolet (DUV) spectral range fabricated with a self-aligned double-patterning process. In contrast to the time-consuming and elaborate measurement techniques like scanning electron microscopy, asymmetry induced quasi-BICs occurring in the near ultraviolet and visible spectral range provide an easily accessible and efficient probe mechanism. Thereby, dimensional parameters are retrieved with uncertainties in the sub-nanometer range. Our results show that BICs are a promising tool for process control in optics and semiconductor technology.

Integrated in situ self-aligned double patterning process with fluorocarbon as spacer layer

Self-aligned double patterning (SADP), or spacer lithography, is a widely used technique in the semiconductor industry for high-throughput nanoscale pattern definition and thus is of great significance for very-large-scale integration, large-area photonic device fabrications, and other applications. In a standard SADP flow, chemical vapor deposition or atomic layer deposition is used to deposit a conformal spacer layer, which is typically a dielectric material. The spacer composition and film quality will influence downstream critical dimension control. However, samples have to go through multiple processing environments, and fabrication complexity is thus increased. In this work, an in situ SADP process is proposed, with all the fabrication steps being integrated into a single process inside a commercially available plasma etching equipment. The spacer layer is a plasma-deposited fluorocarbon film, which has a uniform step coverage and a good etch selectivity to silicon. Various nanostructures have been fabricated to prove the capability of this technique. With its high integrity and technical convenience, this method can be promising to improve the throughput and efficiency of nanofabrication in the semiconductor industry, microelectromechanical systems, and photonic engineering.

Cut Optimization for Redundant Via Insertion in Self-Aligned Double Patterning

Redundant via (RV) insertion helps prevent via defects and hence leads to yield enhancement. However, RV insertion in self-aligned double patterning (SADP) processes is challenging since cut optimization has to be considered together. In SADP, parallel one-dimensional metal lines are divided into signal wires and dummy wires by line-end cuts. If an RV is inserted, signal wires need to be extended to connect to the RV. To this end, an additional cut, which we call RV cut, is introduced to make a space for the extension. Since RV cuts and line-end cuts are manufactured with the same mask set, design rules between those cuts have to be honored, which incurs proper distribution and mask assignment to individual cuts. In this article, we address a problem of integrated RV insertion and cut optimization. We show that the problem can be formulated as an integer linear programming (ILP). We also propose a heuristic algorithm is presented for practical application, in which potential locations of RVs are first identified and used to properly insert as many RVs as possible while minimizing the conflict between RV cuts. Our experimental results demonstrate that 75% of vias receive RVs with 8% increase in total wire length, which is only slightly worse than the optimal result obtained by ILP.

Review of scanning electron microscope-based overlay measurement beyond 3-nm node device

Overlay control has been one of the most critical issues for manufacturing of leading edge semiconductor devices. Introduction of the double patterning process requires stringent overlay control. Conventional optical overlay (Opt-OL) metrology has technical challenges with measurement robustness, solving overlay discrepancy between overlay mark and device pattern, and measuring smaller marks laid out in large numbers within the die accurately for high-order correction. In contrast, scanning electron microscope-based overlay (SEM-OL) metrology can directly measure both overlay targets and actual devices or device-like structures on processed wafers with high spatial resolution. It can be used for reference metrology and optimization of Opt-OL measurement conditions. SEM-OL uses small structures, including actual device patterns, which allows insertion of many SEM-OL targets across a die. Precise overlay distribution can be measured using dedicated SEM-OL mark, improving measurement accuracy and repeatability. To extend SEM-OL capability, we have been developing SEM-OL techniques that can measure not only surface patterns by critical dimension SEM but also buried patterns for leading edge device processes. There are two techniques to detect buried patterns. One is to use high-acceleration voltage SEM, which detects backscattering electron emphasizing material contrast. It has been adopted for overlay measurements for memory and logic devices at after-etch inspection or even after-develop inspection. The other is to utilize charging effect, which reflects voltage contrast at the surface depending on the material properties of underneath structure. SEM-OL measurement using transient voltage contrast has been developed and its capability of overlay measurement has been proven. An overlay measurement algorithm using template matching method has been developed and was applied to dynamic random access memory (DRAM) process monitor in manufacturing. In order to extend SEM-OL metrology to beyond 3-nm node logic and cutting-edge DRAM devices (half pitch = 14 nm), we are improving measurement precision of detecting buried patterns and measurement throughput by developing optimized SEM-OL mark.

Nanofabrication of 10-nm T-shaped gates using a double patterning process with electron beam lithography and dry etch

A process to fabricate T-shaped gates with the footprint scaling down to 10 nm using a double patterning procedure is reported. One of the keys in this process is to separate the definition of the footprint from that for the gate-head so that the proximity effect originated from electron forward scattering in the resist is significantly minimized, enabling us to achieve as narrow as 10-nm foot width. Furthermore, in contrast to the reported technique for 10-nm T-shaped profile in resist, this process utilizes a metallic film with a nanoslit as an etch mask to form a well-defined 10-nm-wide foot in a SiNx layer by reactive ion etch. Such a double patterning process has demonstrated enhanced reliability. The detailed process is comprehensively described, and its advantages and limitations are discussed. Nanofabrication of InP-based high-electron-mobility transistors using the developed process for 10- to 20-nm T-shaped gates is currently under the way.

Statistical Timing Analysis Considering Device and Interconnect Variability for BEOL Requirements in the 5-nm Node and Beyond

In an increasing interconnect resistance era and aggressive metal pitch scaling, the elevating RC delay could significantly shadow the improvements from advanced device architectures and become a severe design issue. This paper will holistically analyze the interplay between transistors and interconnect delay and the variability induced by back-end-ofline (BEOL) process for the 5-nm node. A global sensitivity analysis using Monte Carlo simulation is employed as a powerful tool for understanding the significance of different variation sources and propagating these process uncertainties to circuit performance and parametric yield. For the BEOL integration process, our results show that dielectric κ-value is the most sensitive parameter. Regarding the patterning options, the BEOL process using self-aligned quadruple pattering with positive tone process requires more than a 4× process margin and suffers from 50% parametric yield loss. The required guardband for lithoetch litho-etch becomes as critical as for the self-aligned double patterning process when the overlay control is 6× higher than the critical dimension control. For trench patterning using spacerdefined techniques, a negative tone process is required to achieve a large process window. From a design perspective, the wire length in SoC can be optimized using a disruptive architecture as a vertical FET, which could potentially reduce the average wire length by 11%.

Self-aligned double patterning process for subtractive Ge fin fabrication at 45-nm pitch

The self-aligned double patterning scheme has been developed for subtractive Ge fin patterning targeting critical dimension (CD) <14nm at pitch of 45nm. Compared to the Si self-aligned double patterning route, several modifications have been undertaken in different steps of Ge fin pattering, such as hard mask trimming and main etch. Out of several trimming options, it is the wet trim that has been qualified at the final stage of hard mask CD trimming. It allows meeting CD specifications for all structures and keeping straight lines without wiggling. Finally, the Ge main etch chemistry has been developed, which provides not only a straight fin profile but a flat etching front without depth loading attributed to different density structures.

Line edge roughness frequency analysis during pattern transfer in semiconductor fabrication

Line edge roughness (LER) and line width roughness (LWR) are analyzed based on the frequency domain 3σ LER characterization methodology during pattern transfer in a self-aligned double patterning (SADP) process. The power spectrum of the LER/LWR is divided into three regions: low frequency, middle frequency, and high frequency regions. Three standard deviation numbers are used to characterize the LER/LWR in the three frequency regions. Pattern wiggling is also detected quantitatively during LER/LWR transfer in the SADP process.

Double-side processed III-V nanowire waveguide on a silicon substrate

We introduce a III-V nanowire waveguide structure on a silicon substrate through III-V to silicon adhesive bonding technology. The proposed waveguide structure provides an omni-directional high-refractive-index contrast which is similar to the conventional silicon-on-insulator nanowire waveguides. The optical confinement factor in the active region of the proposed structure nearly doubles that in the conventional hybrid III-V waveguides with a thick p-InP top cladding layer. Electrical injection is also favored in the proposed structure using two thin lateral contact layers which can be fabricated through a double side patterning process. Passive waveguides are fabricated and measured. Propagation losses of 16.18 and 17.83 dB/mm are extracted for the fundamental transverse-electrical and transverse-magnetic modes, respectively, in the proposed III-V nanowire waveguide of 600 nm width.

Gate double patterning strategies for 10-nm node FinFET devices

Amorphous silicon (a-Si) gates with a length of 20 nm have been obtained in a “line & cut” double patterning process. The first pattern was printed with extreme ultraviolet photoresist (PR) and had a critical dimension (CD) close to 30 nm, which imposed a triple challenge on the etch: limited PR budget, high line width roughness, and significant CD reduction. Combining a plasma pre-etch treatment of the PR with the etch of the appropriate hard mask underneath successfully addressed the two former challenges, while the latter one was overcome by spreading the CD reduction on the successive layers of the stack.

Nanochannel fabrication based on double patterning with hydrogen silsesquioxane

A double patterning process is presented to pattern sub-35 nm wide channels in hydrogen silsesquioxane with near 100% pattern densities. Using aligned electron beam lithography, each side of the nanochannel structure is patterned as a separate layer. A 50 000 μC/cm2 high-dose anneal is applied to the first layer after exposure and develop to densify the structure and improve resistance to subsequent chemical exposure. Channels with widths below ∼60 nm are shown to exhibit footing with standard tetramethyl ammonium hydroxide developers. This problem is resolved by adding surfactant during the development of the final channel structure. The resulting process produced channels &amp;lt;35 nm wide with smooth sidewalls and a height of 45 nm.

Ultrahigh density sub-10 nm TiO2 nanosheet arrays with high aspect ratios via the spacer-defined double-patterning process

A novel approach for fabricating ultrahigh-density sub-10 nm TiO2 nanosheet arrays with high aspect ratios by incorporating the spacer-defined double-patterning process with nanoline templates via atom layer deposition (ALD) was demonstrated. A nanoline template can be fabricated readily by pattern transfer from a thin silicon-containing block copolymer film into a thick crosslinked organic polymer layer. The excellent thermal stability of the crosslinked organic template allowed the high-temperature ALD process to deposit the TiO2 thin film conformally on the nanoline template. After the template was removed using dry etching and calcination, a highly crystalline anatase TiO2 nanosheet array with a length of several micrometers was obtained. The thickness of the resulting TiO2 nanosheet could be controlled below half the space of the originally defined nanoline template by incorporating the spacer-defined double-patterning process using ALD. This facile and scalable method could be a useful technique for fabricating ultrahigh-density arrays of various inorganic nanosheets with high aspect ratios.

Reduction of Critical Dimension Difference in Litho-Etch-Litho- Etch Double Patterning Process

Reduction of Critical Dimension Difference in Litho-Etch-Litho- Etch Double Patterning Process

Plasmonic nanoring fabrication tuned to pitch: Efficient, deterministic, and large scale realization of ultra-small gaps for next generation plasmonic devices

A double-patterning process for scalable, efficient, and deterministic nanoring array fabrication is presented. It enables gaps and features below a size of 20 nm. A writing time of 3 min/cm2 makes this process extremely appealing for scientific and industrial applications. Numerical simulations are in agreement with experimentally measured optical spectra. Therefore, a platform and a design tool for upcoming next generation plasmonic devices like hybrid plasmonic quantum systems are delivered.

Novel Clean Concept of Advanced Patterning Film (Amorphous Carbon) for Beyond 2xnm Generation Self-Aligned Double-Patterning (SADP) Process

Advanced Patterning Film (APF, Amorphous Carbon) is newly developed hard mask material by APPLY MATERIALS, Inc. for fine pattern definition, especially used in ArF immersion process. However, amorphous carbon is one candidate of core materials of self align double pattering (SADP) process, usually suggested not to use wet clean process after patter definition due to moisture absorption of APF. We successfully demonstrate better amorphous carbon surface clean performance without any film damaged and line edge roughness (LER) improve 18.2% CD variation, 1.1nm in space even-odd bias beyond 28nm generation. APF of APPLY MATERIALS, Inc. is chemical vapor deposition (CVD) amorphous carbon (a-C) which precursors are normally acetylene (C2H2) and propane (C3H6). Traditional post clean SPM chemical consists of sulfuric acid (H2SO4) and hydro peroxide (H2O2). Hydro peroxide will oxidize amorphous carbon into CO or CO2and result in pattern damaged. We surveyed some post clean candidates in semiconductor fabrication common used, as table 1 shows. Only APM and DHF showed miner or no etching rate to amorphous carbon film. APM is first chosen chemical for amorphous carbon core post etching clean. In Figure 1-a, 3nm/side etching polymer is found on a-C sidewall, and Figure 1-b shows that dry etching polymer are totally removed after APM 10 minutes treatment. However, in SADP process, core material should be with higher removal rate than spacer material, which is usually selected by high temperature deposition film to achieve the high selectivity to core material in core removal process.As Figure 2 shows, amorphous carbon with C2H2precursor is porous structure. 10 minutes APM process will induce moisture absorption by porous amorphous carbon film and line twist in following high temperature spacer material deposition, 450C atomic layer deposition silicon nitride, shows as Figure 3-a. Figure 3-b shows worse even-odd spacer bias after SADP spacer defined. Shorter clean process time and high clean efficiency become the keys of a-C core post clean step. Two chemicals A and B, A is higher fluorine concentration contained and B is lower fluorine concentration contained, a-C core post clean efficiency were investigated and both process times are confined within 90 seconds, including rinse and drying steps. Figure 4-a., 4-b. and 4-c show chemical A has better polymer removal capability than chemical B. Line edge roughness (LER) is reduced from 3.03nm to 2.48nm, 18.2% improvement, shows as Figure 5. In Figure 6 good LER and even-odd space performance of SADP gate definition after adopting chemical A for a-C post etching clean. Long time clean process will result in water absorption of amorphous carbon film due to its porous structure, and will cause worse line edge roughness (LER) in the following high temperature spacer material deposition process. Shorten clean process time to avoid water absorption and improve clean efficiency are the major criteria to achieve successful amorphous carbon clean. Novel a-C clean method by raising F concentration to achieve higher clean efficiency and successfully improve LER 18.2% after core etching and post clean in positive tone SADP process beyond 2xnm generation.