Double Heterojunction Bipolar Transistor Technology Research Articles

Transmitter and Receiver Circuits for a High-Speed Polymer Fiber-Based PAM-4 Communication Link.

A high data rate RF-DAC and a power detector (PD) are designed and fabricated in a 250 nm indium phosphide (InP) double heterojunction bipolar transistor (DHBT) technology. A communication link using the Tx-Rx over polymer microwave fiber (PMF) is measured. The link consists of a pulse amplitude modulation (PAM) modulator and a PD as a demodulator, as well as a one-meter-long dielectric waveguide. The working frequency range of the complete link is verified to be 110–150 GHz. The peak output power of the PAM modulator is 5 dBm, and it has a −3 dB bandwidth of 43 GHz. The PD consists of a parallel connected common emitter configured transistor and a common base configured transistor to suppress the odd-order harmonics at the PD’s output, as well as a stacked transistor to amplify the output signal. Tx and Rx chips, including pads, occupy a total area of only 0.83 mm2. The PMF link can support a PAM-4 signal with 22 Gbps data transmission, and a PAM-2 signal with 30 Gbps data transmission, with a bit error rate (BER) of <10−12, with demodulation performed in real time. Furthermore, the energy efficiency for the link (Tx + Rx) is 4.1 pJ/bit, using digital data input and receiving PAM-2 output (5.6 pJ/bit for PAM-4).

A 32.2 GHz Full Adder Designed with TLE Method in a InP DHBT Technology

Ultra-high-speed full adder is the bottleneck in a tens of GHz Direct digital synthesizer (DDS). In this paper, a 32.2 GHz, 1bit full adder in a 0.7 μm InP double hetero-junction bipolar transistor (DHBT) technology is presented. In such a high-speed circuit, signal integrity is a crucial issue. Therefore, a transmission line equivalent (TLE) method is proposed. With the TLE method, the design of the full adder could be simplified with good accuracy. The synchronous latch is combined with adding operation to improve the calculation speed. A single-level parallel-gated circuit is designed using majority decision algorithm to reduce power consumption. Measurement results show that the maximum clock frequency of the full adder is 32.2-GHz, and the overall power consumption is 350 mW. The full adder is successfully adopted in a 17 GHz, 8 bit DDS which can synthesize sin-wave outputs from 66.41 MHz to 8.5 GHz in 66.41 MHz steps with an average Spurious-Free Dynamic Range (SFDR) of -18.1 dBc.

106‐GHz bandwidth InP DHBT linear driver with a 3‐V ppdiff swing at 80 GBd in PAM‐4

This Letter reports the design, fabrication and characterisation of a new differential linear driver, fabricated in the III-V Lab 0.7- emitter width indium phosphide (InP) double heterojunction bipolar transistor (DHBT) technology. Large-signal electrical characterisation shows 80-GBd symbol-rate four-level pulse amplitude (PAM-4) modulation conjugated with a driver output swing of 3-Vppdiff and a 0.74-W power consumption. Thus resulting in a 1.22-GBd driving efficiency, the highest in over 70-GBd drivers' state-of-the-art, at that date. Accordingly, S-parameter measurements of the standalone linear driver exhibit the highest gain-bandwidth product of 556 GHz, in that current state-of-the-art.

Nongalvanic Generic Packaging Solution Demonstrated in a Fully Integrated D-Band Receiver

This article presents a packaging technique for monolithic microwave integrated circuits (MMIC) demonstrated in a fully integrated receiver (Rx) module at the D -band (110–170 GHz). The solution consists of an MMIC-to-waveguide transition realized using an on-chip probe mounted in the E -plane of a split-block waveguide module. An artificial magnetic conductor structure is implemented to suppress cavity modes and achieve better coupling from the waveguide to the probe. The transition's performance is experimentally verified using a back-to-back test chip, and measurement results show that the proposed packaging solution achieves a low insertion loss of only 0.7 dB and covers a very wide frequency range extending from 105 to 175 GHz. The proposed transition is also integrated with an in-phase/quadrature-phase (I/Q) Rx on the same chip. The Rx is realized in a 250-nm indium phosphide double heterojunction bipolar transistor technology and consists of a low-noise amplifier, an I/Q mixer, and a frequency tripler. Measurement results show that the Rx module achieves an average conversion gain of 23 dB across the frequency range of 110–145 GHz and has an average noise figure of 10.6 dB. The Rx MMIC has a dc power consumption of 440 mW and occupies an area of 1.6 × 1.6 mm2. This article addresses one of the main challenges in systems operating above 100 GHz and presents a fully integrated packaging solution that suits large integrated circuits and does not require any galvanic contacts nor impose any limitations on MMIC dimensions.

A 300-GHz High-Power High-Efficiency Voltage-Controlled Oscillator With Low Power Variation

This letter presents a 300-GHz voltage-controlled oscillator (VCO) with high output power and efficiency. The VCO core employs a differential Colpitts topology with inductive degeneration to facilitate a fundamental oscillation at 300 GHz. A common-base output buffer regulates the output power to minimize the power variation during the frequency tuning. The 300-GHz VCO is fabricated in a 130-nm InP double heterojunction bipolar transistor (DHBT) technology. The VCO exhibits a measured frequency tuning range of 9.9 GHz (294.9–304.8 GHz). The peak output power is measured to be 4.7 dBm at 297 GHz. The dc power consumption is 75.6 mW, leading to a high dc-to-RF conversion efficiency of 3.9%. The VCO output power is maintained nearly constant with only a 0.3-dB variation over the entire frequency tuning range. The phase noise is −86.6 dBc/Hz at 10-MHz offset frequency.

300‐GHz integrated heterodyne receiver with carrier lock‐in Costas loop

A carrier signal lock-in experiment using a 300-GHz integrated heterodyne circuit is presented. The circuit contains a single voltage-controlled oscillator with a single set of quadrature mixers that are fabricated using 250-nm InP double hetero-junction bipolar transistor technology. An external feedback loop containing packaged baseband components such as amplifiers, a phase discriminator, and a filter is connected to the integrated circuit to form a complete receiver system. For a −25 dBm of input RF signal with 3.5-GHz single-tone carrier-suppressed modulation, the receiver system responds with successful lock-in range of 110 MHz centred around 311 GHz.

Performance Analysis of a Low-Noise, Highly Linear Distributed Amplifier in 500-nm InP/InGaAs DHBT Technology

This article is an extension of the previous report on an ultrawideband distributed amplifier (DA) in the InP double heterojunction bipolar transistor (DHBT) technology. With the choice of a tricode unit cell, the Miller capacitance is reduced and a larger bandwidth (BW) is obtained. Measured S-parameters show a 3-dB BW of near dc to >170 GHz with a gain of 12 dB. In addition, the circuit operates in low dc bias conditions, thus yielding a low measured noise figure (NF) of 8 dB over the frequency range of 5–50 GHz and 12 dB at 135 GHz. Within the 5–50-GHz frequency range, the NF is only 0.5 dB higher than the NF of a similar DA with cascode unit cell. When the circuit is measured for large-signal condition, it reaches a 1-dB output compression point, $P_{\mathrm {1\,dB}}$ , of 8.4 dBm at 150 GHz, a saturated output power of approximately 10 dBm, and an associated maximum power-added efficiency (PAE) of 6%. This is the best linearity as well as the highest saturated output power and PAE reported at this frequency for DAs. When measured at 20 GHz, the circuit shows a $P_{\mathrm {1\,dB}}$ , of 9 dBm and output referred third-order intercept point of 22 dBm, a saturated output power of 11 dBm, and an associated maximum PAE of 6%, thereby proving its uniform large-signal character within the full band. In short, this circuit brings in the unique combination of low NF, highly linear characteristics, and high PAE simultaneously together over large BW. Furthermore, the circuit consumes 180 mW of dc power only.

Design and modeling of an ultra-wideband low-noise distributed amplifier in InP DHBT technology

AbstractThis paper reports on an ultra-wideband low-noise distributed amplifier (LNDA) in a transferred-substrate InP double heterojunction bipolar transistor (DHBT) technology which exhibits a uniform low-noise characteristic over a large frequency range. To obtain very high bandwidth, a distributed architecture has been chosen with cascode unit gain cells. Each unit cell consists of two cascode-connected transistors with 500 nm emitter length and ft/fmax of ~360/492 GHz, respectively. Due to optimum line-impedance matching, low common-base transistor capacitance, and low collector-current operation, the circuit exhibits a low-noise figure (NF) over a broad frequency range. A 3-dB bandwidth from 40 to 185 GHz is measured, with an NF of 8 dB within the frequency range between 75 and 105 GHz. Moreover, this circuit demonstrates the widest 3-dB bandwidth operation among all reported single-stage amplifiers with a cascode configuration. Additionally, this work has proposed that the noise sources of the InP DHBTs are largely uncorrelated. As a result, a reliable prediction can be done for the NF of ultra-wideband circuits beyond the frequency range of the measurement equipment.

Transimpedance amplifiers with 133 GHz bandwidth on 130 nm indium phosphide double heterojunction bipolar transistors

In this work, the authors present two transimpedance amplifier (TIA) circuits designed for fibre optical interconnect systems. They compare a common base (CB) topology with a common emitter (CE) shunt shunt feedback topology in terms of frequency response, power consumption, noise, and input impedance. The two TIAs are designed on a 130 nm indium phosphide double heterojunction bipolar transistor technology from Teledyne Scientific Company (TSC) with an 1 f(t)/f(max). of 520 GHz/1.15 TED and are measured in the frequency and time domains. They exhibit a transimpedance gain of 42 dBS2 with a 133 GHz bandwidth, the highest bandwidth reported in the literature and power consumption of 32.3 nikV tqr the C13 and 25.5 mW for the CE. Eye diagram measurements were conducted up to 64 Ghps and input referred noise density was measured at 30.2 pAh/root Hz for the CB and 13.9 pA.root Hz for the CE.

180 to 240 GHz broadband, EM‐based power amplifier using 0.5‐μm InP DHBT technology

AbstractThis paper reports a power amplifier (PA) terahertz monolithic integrated circuit (TMIC) from 180 to 240 GHz. This amplifier is fabricated from a 0.5‐μm indium phosphide double heterojunction bipolar transistor (InP DHBT) technology, jointly with a thin‐film microstrip wiring environment. Furthermore, an electromagnetic (EM) simulation method is proposed for the parameter extraction of InP DHBTs and amplifier design. This five‐stage amplifier has &gt;6.1 dB S21 gain from 180 to 240 GHz, peaks 10.4 dB S21 gain at 210 GHz. At 213 GHz operation, the saturated output power is 5.8 dBm with 7.3 dB large‐signal gain, and this amplifier occupies 2.52 mm2 including pads.

212‐Gbit/s 2:1 multiplexing selector realised in InP DHBT

In this Letter, the authors report on the design, optimisation and electrical measurements of a new fully integrated multiplexing selector fabricated in 0.7-mu m indium phosphide (InP) double-heterojunction bipolar transistor technology. All parts of the circuit were optimised to obtain 200-Gbit/s class of operation. They present electrical performances at 140 and to a record speed of 212 Gbit/s, highlighting their respective measurement challenges. The power consumption of the circuit is 0.5 and 0.8 W for a differential output amplitude of 240 and 730 mV, respectively. This selector has been successfully used as modulator driver in optical transmission experiments up to 204 Gbit/s.

E‐band Indium Phosphide double heterojunction bipolar transistor monolithic microwave‐integrated circuit power amplifier based on stacked transistors

AbstractA monolithic microwave‐integrated circuit 2‐stage power amplifier (PA) realized in indium phosphide double heterojunction bipolar transistor technology is presented in this article. The 2‐ and 3‐stacked transistors are used in the driver and power stages, respectively. As a mean to increase the output power capabilities, 2‐ and 4‐way corporate power combiners are implemented in coplanar waveguide technology. The fabricated PA exhibits a small‐signal gain of 13.6 dB at 77 GHz and a 3‐dB bandwidth ranging from 74 to 86 GHz. At 78 GHz, the saturated output power is &gt;19.6 dBm.

A Highly Efficient Ultrawideband Traveling-Wave Amplifier in InP DHBT Technology

This letter presents a 1 to >110-GHz ultrawideband traveling-wave amplifier (TWA) based on 500-nm transferred-substrate InP double-heterojunction bipolar transistor technology. The HBT cells are realized with inductive peaking at the output and match the phase delay between individual stages. The collector bias is slightly below the value for the maximum current gain. This allows a frequency-invariant high-output power characteristic with a flat group delay. The amplifier exhibits a gain of 13 dB with a measured bandwidth of 1–110 GHz and a uniform 10-dBm 1-dB compression output power with an associated maximum PAE of 8% at 110 GHz. To the best of our knowledge, this is the highest PAE and the maximum flat output power reported for such a TWA covering frequencies up to 170 GHz. The amplifier consumes only 129 mW, which is among the lowest dc power dissipations reported for the given gain–bandwidth product. Moreover, the group delay is flat across the band, which makes the TWA very useful in high-speed optical communication systems.

Design and Analysis of a Wideband Gilbert Cell VGA in 0.25- $\mu {\rm m}$ InP DHBT Technology With DC-40-GHz Frequency Response

A differential variable gain amplifier (VGA) for wideband baseband signals has been designed, analyzed, and implemented in a 0.25- $\rm \mu m$ InP double heterojunction bipolar transistor technology with $f_{T}/f_{\mathrm{ max}}$ of 370/650 GHz. The 3-dB frequency bandwidth is measured to be 40 GHz with a maximum gain of 31 dB, resulting in a gain bandwidth product (GBP) of 1.4 THz, four times higher than previously reported GBP from a Gilbert cell-based VGAs. Furthermore, it measures a gain control range of 44 dB, a noise figure of 6.2 dB, an output third-order intercept point of 17 dBm, and a total power consumption of 350 mW from a single −7-V supply. With pseudorandom binary sequence test pattern signals, a clear open eye at 44 Gb/s was observed. The complete circuit, including on-chip integrated bias network and pads, measures 0.77 $\rm mm^{2}$ . We analyze the VGA for the 3-dB bandwidth and GBP by the use of zero-value time constants method to analytically identify the maximum GBP with respect to the design parameters and current bias.

InP DHBT technology for power amplifiers at mm-wave frequencies

An InP Double Heterojunction Bipolar Transistor (DHBT) technology is presented for millimeter-wave power amplifiers at E-band and higher frequencies. Single- and multi-finger transistors with 0.7μm emitter width and emitter lengths of 5, 7, 10μm are designed for high frequency and high power applications. The static and AC performances of the fabricated devices are discussed. Reported cutoff frequency and maximum oscillation frequency are ft=267GHz and fmax=450GHz for a 0.7×5μmP2 single-finger device, respectively. Results from large-signal measurements at 30GHz are reported for single and 4-finger devices. Ballasted devices are introduced to improve thermal behaviour and to increase the limits of the safe operating area (SOA). The SOA is improved approximately by 75% for 4-finger devices with 0.7×10μm2 emitter. A fabricated monolithic microwave integrated circuit (MMIC) at E-band based on stacked InP DHBTs is presented and its performances reported to demonstrate the power capabilities of the technology.

A 280-GHz InP DHBT Receiver Detector Containing a Differential Preamplifier

A power detector integrated with a preamplifier is fabricated using a 250-nm InP double-heterojunction bipolar transistor technology for 280-GHz operation. The input RF signal to the detector is modulated at 20 kHz to decouple the output dc voltage from 1/f noise. The integrated receiver detector consists of a two-way balun, a differential preamplifier, a power detector. Breakout circuits of a standalone power detector and a test amplifier have been independently characterized. The test amplifier shows a gain of 18.1 dB and noise figure of 14 dB. The responsivity and noise equivalent power of the detector improve from 4.5 to 350 kV/W and from 10 to 0.13 pW/Hz0.5, respectively, at 280 GHz, with the addition of the preamplifier. The performance enhancements due to the preamplifier are in close agreement with the results predicted by advanced design system simulations.

A -Band 48-Gbit/s 64-QAM/QPSK Direct-Conversion I/Q Transceiver Chipset

This paper presents design and characterization of single-chip 110–170-GHz ( $D$ -band) direct conversion in-phase/quadrature-phase (I/Q) transmitter (TX) and receiver (RX) monolithic microwave integrated circuits (MMICs), realized in a 250-nm indium phosphide (InP) double heterojunction bipolar transistor (DHBT) technology. The chipset is suitable for low-power ultrahigh-speed wireless communication and can be used in both homodyne and heterodyne architectures. The TX consists of an I/Q modulator, a frequency tripler, and a broadband three-stage power amplifier. It has single sideband (SSB) conversion gain of 25 dB and saturated output power of 9 dBm. The RX includes an I/Q demodulator with $D$ -band amplifier and $\times$ 3 multiplier chain at the LO port. The RX provides a conversion gain of 26 dB and has noise figure of 9 dB. A 48-Gbit/s direct quadrature phase-shift keying (QPSK) data transmission using a 144-GHz millimeter-wave carrier signal is demonstrated with a bit error rate (BER) of 2.3 $\,\times \hbox{ 10} ^{-3}$ and energy efficiency of 7.44 pJ/bit. An 18-Gbit/s 64-quadrature amplitude modulation (QAM) signal was transmitted in heterodyne mode with measured TX-to-RX error vector magnitude (EVM) of less than 6.8% and spectrum efficiency of 3.6 bit/s/Hz. The TX and RX have dc power consumption of 165 and 192 mW, respectively. The chip area of each TX and RX circuit is 1.3 $\,\times\,$ 0.9 $\hbox{mm}^{2}$ .

A G-band terahertz monolithic integrated amplifier in 0.5-μm InP double heterojunction bipolar transistor technology**Project supported by the National Natural Science Foundation of China (Grant No. 61501091) and the Fundamental Research Funds for the Central Universities of Ministry of Education of China (Grant Nos. ZYGX2014J003 and ZYGX2013J020).

Design and characterization of a G-band (140–220 GHz) terahertz monolithic integrated circuit (TMIC) amplifier in eight-stage common-emitter topology are performed based on the 0.5-μm InGaAs/InP double heterojunction bipolar transistor (DHBT). An inverted microstrip line is implemented to avoid a parasitic mode between the ground plane and the InP substrate. The on-wafer measurement results show that peak gains are 20 dB at 140 GHz and more than 15-dB gain at 140–190 GHz respectively. The saturation output powers are −2.688 dBm at 210 GHz and −2.88 dBm at 220 GHz, respectively. It is the first report on an amplifier operating at the G-band based on 0.5-μm InP DHBT technology. Compared with the hybrid integrated circuit of vacuum electronic devices, the monolithic integrated circuit has the advantage of reliability and consistency. This TMIC demonstrates the feasibility of the 0.5-μm InGaAs/InP DHBT amplifier in G-band frequencies applications.

84 GBd (168 Gbit/s) PAM‐4 3.7 V pp power DAC in InP DHBT for short reach and long haul optical networks

The architecture and performances of a multilevel driver for pulse amplitude modulation (PAM) formats, designed and fabricated in 0.7 µm InP double-heterojunction bipolar transistor technology, are reported. The driver part is based on a power-DAC architecture which is integrated with the multiplexing stage composed of three 2:1 selectors. Up to 100 GS/s operation was validated and PAM-2, -4, -8 signals with high amplitude were measured. In particular, PAM-4 at 84 GBd and PAM-8 at 64 GBd operation was demonstrated with, respectively, a 3.7 and 4 Vpp differential output signal. This compact driver circuit is characterised by the highest merit factor in terms of high amplitude and the transmission capacity for an electronically generated multilevel signal.

In brief

PAGE 1615 An algorithm using backlog information for slot allocation in satellite-based sensor systems based on Quality of Service (QoS) fairness has been developed by a team from China. The group used delay performance as a measure of QoS, and focussed on long term rather than short term fairness. PAGE 1584 A group based in Germany have used liquid crystal as a tuneable dielectric material to produce a continuously tuneable substrate integrated waveguide band pass filter. The device has a high Q-factor comparable to substrate integrated waveguides with other types of tuneable material, but achieves operating frequencies ten times as high. Simulations show that the system could improve performance by at least 10% PAGE 1587 Authors from the USA present a useful document on achieving and maintaining two decades of bandwidth with monolithic microwave integrated circuit (MMIC) distributed amplifiers. According to the authors, achieving this level of performance can be difficult even when suppliers indicate it can be achieved with their devices. The filter is continuously tuneable within a tuning range of 610 MHz PAGE 1563 Using leather as a substrate, a team from India have designed and fabricated a tri-band substrate integrated waveguide based antenna. The antenna, which uses a combination of conducting and non-conducting leather materials, is compact and flexible, and directs radiation away from the user. The paper also outlines ways to improve devices with lower performance PAGE 1591 The performances and architecture of a multilevel driver for Pulse Amplitude Modulation (PAM) formats is reported on by a team based in France and the USA. The device is designed and fabricated in InP double-heterojunction bipolar transistor technology, and is developed for short reach and long haul networks. The antenna is designed for use in the ISM, WiMAX and Military Applications bands The device can generate PAM-2, PAM-4 and PAM-8 outputs