Double-gate Research Articles

Design Considerations into Circuit Applications for Structurally Optimised FinFET

FinFETs have gained a lot of demand in the family of multigate FET devices in the recent years. In this view, this manuscript aims to design different FinFET architectures to observe the analog and circuit performance. A total of five structures namely Conventional FinFET, Lightly doped S/D, Underlap FinFET, Single-k spacer, and Dual-k spacer FinFET has been designed and performance has been analysed. The best performance is obtained for dual-k spacer FinFET. Moreover, the dimensional variations such as gate length (Lg), fin width (Wfin) and fin height (Hfin) for the duak-k spacer FinFET is performed and it is found that lowering the Lg and Wfin, and increasing the Hfin would be a better option in order to enhance the device performance. Furthermore, at the optimized device dimensions the circuit analysis for inverter and single stage common source amplifier is performed. The gain for the designed single stage common stage amplifier is noticed to be 1.8155.

3차원 집적 유연 인쇄 전자: 집적 회로, 메모리, 센서

Printing technologies have received a lot of attention and expectations for producing flexible and wearable electronics. However, the low transistor density of the printed devices has been a major obstacle to commercialization. In this review, a three-dimensional (3D) integration of organic flexible and printed electronics is described. First, layout-to-bitmap conversion and design rules for printed transistors, arrays, and integrated circuits are introduced. Then, printed 3D transistors, digital integrated circuits, and memories are described. Finally, 3D integration of printed active-matrix arrays and sensors is highlighted. This approach is a breakthrough technology that not only reduces the area occupied by a single transistor, memory, and sensor, but also increases the efficiency of routing, effectively reducing the area of the entire devices. In addition, monolithic 3D integration through the printing can stack transistor, memory, and sensor by simply repeating the additive process.

Optical Performance of the Double Gate Reverse T-Shaped Channel TFET in Near Visible Light Photodetector

Optical Performance of the Double Gate Reverse T-Shaped Channel TFET in Near Visible Light Photodetector

Performance evaluation of split high–K material based stacked hetero-dielectrics tunnel FET

This research investigates the performance evaluation of a double gate TFET (DGTFET) by employing a hetero-dielectric gate structure featuring distinct high-K dielectrics with different work functions in a dual-material gate configuration. The gate dielectric stack is comprised of split high–K materials placed on the SiO2 dielectric. An outline of the analytical model for the validation of the novel device is developed and 2D simulations-based analysis and investigation are carried out. The impact of different high-K dielectric materials layered on top of silicon dioxide (SiO2) is examined; its effect on transfer characteristics, subthreshold swing (SS), minimum tunneling width, ratio of ON to OFF currents ION/IOFF, and energy band bending are investigated. The work functions optimization for the auxiliary and tunnel gates are made in this work to minimize OFF current, to reduce ambipolar phenomena and to enhance tunnel rate. The effects of gate potentials, source/ drain doping concentrations on the results are further studied. The threshold voltage of DGTFET is also modelled and computed for the proposed structures. The present findings revealed that the low OFF current (10−17 A μm−1) is provided by the proposed device structure, improved ratio of ION/IOFF (1011), and lowered subthreshold swing required for future era.

Emulation of neuro-mimetic dynamics via GaSb/Si heterojunction V-DGTFET leaky-integrate-fire silicon neuron

A leaky integrate and fire (LIF) neuron property is emulated using vertically developed double gate GaSb/Si tunnel field effect transistor (V-DGTFET). The suggested device can precisely replicate the neuronal dynamics after considering and proper validating the numerical simulations. Silvaco-TCAD tool is exploited for emulation of neuronal attributes and found in good agreement with earlier published research data. The article reports the membrane threshold voltage of 0.47 V which is 3.2x, 2.13x, 2.13x, 1.28x times less as compared to silicon nanowire, MOSFET, phase change device and Bulk FinFET neuron. The energy required for mimicking the neurons is computed as 0.748 aJ which is 1.2 × 109, 4 × 107, 4.68 × 107, 1.34 × 107, 7.59 × 106, 8.42 × 103, 4.30 × 103 3.34 × 105, 2.41 × 105, 1.52 × 106, 26.7,2, 3.88 × 103 times less compared to CMOS, phase change device, SOI CMOS, PCMO RRAM, SiNPN, Bulk FinFET, BTBT based PDSOI MOS, FBFET, LBIMOS, DGJLFET, Si NIPIN, DL-TFET, silicon nano wire respectively. The biasing at second gate is used to induce potential well at channel region to accumulate hole carriers produced due to impact ionization. The threshold current is achieved at 0.20 V drain voltage which is 15x, 14x, 10x, and 1.5x less as compared to FinFET, PD-SOI MOSFET, LBIMOS, and DLTFET respectively. Furthermore, calculated spiking frequency of V-DGTFET LIF neuron is 534 GHz. Thus, remarkable enhancement in frequency of operation and an ultra-low energy per spike makes this neuron device a potential solution for implementing the neuro-mimetic behaviour at large scale.

Sensitivity analysis of TMD TFET based photo-sensor for visible light detection: A simulation study

This paper reports the sensitivity analysis of double gate TFET using the Transition Metal Di chalcogenide (TMD) material in photo sensitive region with the help of technology computer aided design (TCAD) simulator tool. The sensitivity analysis elaborates the significance of TMD material for optical applications. The photo sensitivity analysis is exhibited for the variation in wavelength (λ) of incident light under the visible range of spectrum. Furthermore, we have executed the performance of photo sensor by varying the position of illumination window. Result reveals that sensitivity, responsivity, and quantum efficiency of sensor are improved at λ = 320 nm. The maximum value of signal to noise ratio (SNR) and responsivity (R) are 63.2 dB and 106, respectively, under the visible range. This TMD material based TFET photo-sensor will be useful for the next generation low power highly sensitive optical devices.

Impact of back gate-drain overlap on DC and analog/HF performance of a ferroelectric negative capacitance double gate TFET

In this manuscript, we present a negative capacitance TFET with extended back gate-drain overlap (DEBG-NC-TFET) to enhance DC and analog/high frequency (HF) performance. TCAD-based simulations reveal that DEBG-NC-TFET offers a significant enhancement in ION and SS because of a Ferroelectric (FE) layer introduced into the gate-oxide layer of the device, without deteriorating its other parameters. This work examines the effects of various factors of NC including coercive electric field (Ec) and remnant polarization (Pr) on memory window (MW) to improve the read margin of the device. With an optimum thickness of FE layer, DEBG-NC-TFET is found to offer a huge reduction in the ambipolar current (Iamb) with unchanged IOFF and ION as compared with those of symmetric gate-drain overlap (DSYG) and conventional DG-NC-TFET. The vertical component of the field induced inside the drain region increases the layer of depleted charge at the channel-drain interface, which enhances the barrier width and restricts the charge carriers from tunneling at the ambipolar state. Furthermore, incorporating back gate-drain overlap into DG-NC-TFET resolves the trade-off between parasitic capacitances and ambipolarity as overall gate capacitance is found to be reduced for DEBG-NC-TFET. Apart from reduction in gate parasitic capacitance, various HF parameters like gain–bandwidth product (GBWP) and cutoff-frequency (fT) are also found to be improved for DEBG-NC-TFET as compared to DSYG-NC-TFET. Finally, a resistive load inverter analysis shows that various parameters like propagation delay, full swing, and peak over- and undershoots are significantly improved when only the back gate overlaps the drain region of DG-NC-TFET.

Doping-less MultiGate Inverted-T shape FET device with Schottky source/drain contacts

A dopingless multi-gate inverted-T Shape device has been proposed with Schottky source/drain contacts. Gate oxide engineering is performed on the proposed device, and its two configurations namely Hetero-Dielectric (HD) and Gate-Stack (GS) are implemented. The proposed HD configuration of dopingless inverted-T shape FET has asymmetric oxide; where oxide (HfxTi1-xO2) having high value of dielectric is placed on source side and SiO2 with lower dielectric value is placed on drain side. The designed device showcase a leakage current of approximately 10−16 A in contrast to the traditional junctionless FET which has leakage of 10−10 A. Also, comparative analysis of the GS and HD dopingless multi-gate inverted-T shape transistor is outlined at different parameters including channel length, fin width and Ultra-thin body thickness. AC analysis of the device has been done to evaluate cut-off frequency and gain bandwidth product. Additionally, p-channel configuration is formulated in conjunction with n-channel MOS configuration to investigate the device's suitability for applications employing CMOS technology.

Effects of metal work function and gate-oxide dielectric on super high frequency performance of a non-align junction DG-MOSFET based inverter in the sub-100 nm regime: a TCAD simulation analysis

ABSTRACT This paper presents simulation analysis of an inverter made from non-aligned double gate field effect transistors (NADGFETs) in Sub-100 nm regime. The inverter consists of n-channel NADGFET and p-channel NADGFET device with a channel length of 40 nm and 50% non-alignment between gate and source/drain. The response of the inverter was tested by a combination of gate dielectric constant (k) and metal work function (ϕ). Three gate dielectrics namely, SiO2 (k = 3.9), Si3N4 (k = 7.2), HfO2 (k = 24), and three metal work function namely tungsten (ϕ = 4.5 eV), molybdenum (ϕ = 4.75 eV), gold (ϕ = 5 eV), were considered in the NADGFET inverter. This paper defines a kϕ index as characterising parameter to explore the best response from inverter configuration with minimum propagation delay, and minimum power consumption at super-high frequency. The paper proposes to analyse the NADGNFET device, in term of ION current, ION/IOFF ratio, cut-off frequency, and gate delay. And observes that low k material with moderate metal work function gives best response. The work then simulates the inverter and group the results into voltage transfer curve (VTC), transient response, and power dissipation category. The result shows that when inverter was subjected to high frequency, all the kϕ combination responds good, however when the inverter was subjected to super-high frequency, the low value of kϕ combination performs well. Thus, the result concludes that SiO2-M2 combination will be best selection to get minimum propagation delay and dynamic power dissipation by the inverter. The test strategy presented in this paper on the basis of kϕ index can serve as benchmark to test inverter device at super-high frequency.

Drain current sensitivity analysis using a surface potential-based analytical model for AlGaN/GaN double gate MOS-HEMT

In this research, a surface potential-based drain current model for an AlGaN/GaN symmetrical double-gate metal oxide semiconductor high electron mobility transistor (DG-MOSHEMT) is proposed and used to detect label-free biomolecules for the first time. The model is applied for a nanocavity-based DG-MOSHEMT and works on the concept of dielectric modulation to detect biomolecules like uricase, urease, streptavidin, protein, biotin, ChOx, and APTES(3-aminopropyltriethoxysilane). The performance indicators, such as a change in drain ON current (ΔION), drain current sensitivity (SION), transconductance sensitivity (Sgm), and output conductance sensitivity (Δgd), are used to assess the device's efficacy. Numerical simulations are conducted to verify the model's accuracy and quantify its sensitivity. The DG-MOSHEMT device elicited exceptional sensitivity towards the uricase biomolecule, surpassing all other analytes tested, with SION = 0.328, Sgm = 0.197, and Δgd = 28.1 mS/mm. Furthermore, the model considers the contribution of the first two sub-bands of the quantum well and competently captures the fluctuation in drain ON current and sensitivity. A comprehensive sensitivity analysis of the drain current is conducted by altering physical parameters such as cavity length, thickness, gate length and barrier layer thickness. Notably, the sensitivity SION is significantly improved with cavity length and thickness for the optimized AlGaN barrier layer.

Simulation study on quantum dot formation of double-qubit-Si-MOS device

Silicon quantum dots (QDs) are essential physical carriers of quantum bits (qubits) in quantum computing. However, their extremely small size renders them highly sensitive to both the fabrication process and surrounding environment. Accuracy and stability must be carefully considered. In this study, we propose a double gate QD device model based on silicon metal-oxide-semiconductor (Si-MOS) for the generation of spin qubits. Using a Technology Computer Aided Design (TCAD) simulation, we investigated the impact of device dimensions, including oxide layer thickness, channel length, and spacer length, on the QD structure. Additionally, we examined the effects of the temperature and interface trap concentration on QD formation. An equivalent circuit model was employed to assess the charging energy (Ec) of QDs. Our results demonstrate that by appropriately adjusting these parameters, it is possible to achieve a QD structure with a wide level spacing and small size capable of accommodating as few as four electrons. Furthermore, we calculated an Ec of 33 meV for the QDs.

MoS2-Based Dual-Gate mosfet as Ultrasensitive SARs-CoV-2 Biosensor for Rapid Screening of Respiratory Syndrome

MoS₂-Based Dual-Gate mosfet as Ultrasensitive SARs-CoV-2 Biosensor for Rapid Screening of Respiratory Syndrome

Threshold and surface potential-based sensitivity analysis of symmetrical double gate AlGaN/GaN MOS-HEMT including capacitance effects for label-free biosensing

This paper presents an analytical framework, based on the surface potential for a symmetrical double-gate AlGaN/GaN Metal oxide semiconductor high electron mobility transistor (DG-MOSHEMT) equipped with an embedded nanocavity tailored for biomedical sensing applications. The proposed model operates on the dielectric modulation principle and meticulously scrutinizes the device’s performance using critical sensing metrics such as threshold voltage shift (ΔVth), threshold voltage sensitivity (SVth), surface potential shift (ΔΨs,0), and surface potential sensitivity (SΨs,0). The model demonstrates remarkable sensitivity in detecting minute biomolecule variations, explicitly focusing on streptavidin, uricase, protein, and ChOx as the target biomolecules. Additionally, analytical equations based on surface potential are established to accurately determine gate charges (QG), gate-to-drain capacitance (CGD), and gate-to-source capacitance (CGS). The thorough investigation of biomolecule effects on gate capacitance holds paramount significance as it plays a vital and profound role in dictating device performance. Furthermore, variations in nanocavity length, AlGaN layer thickness, and oxide layer thickness are explored to understand their influence on ΔVth and SVth. The proposed model exhibits a remarkable improvement in both threshold voltage shift and sensitivity compared to the single MOS-HEMT. Notably, it demonstrates substantial enhancements of 2.06, 1.72, 1.49, and 1.5 times for the uricase, streptavidin, protein, and ChOx biomolecules, in terms of threshold voltage shift, and impressive improvements of 10.7%, 14.5%, 18.2%, and 50% for the same biomolecules, respectively, in terms of threshold voltage sensitivity, surpassing the previous findings. Uricase exhibited the most significant shift in surface potential (ΔΨs,0) among the analyzed biomolecules, with a value of 100 mV mm−1 and a sensitivity (SΨs,0) of 0.44. In contrast, ChOx showed a modest (ΔΨs,0) of 24 mV mm−1 with a relative sensitivity (SΨs,0) value of 0.108. Increasing nanocavity length and oxide layer thickness positively contribute to ΔVth and SVth. Moreover, while an increase in AlGaN layer thickness enhances ΔVth performance, its impact on SVth is minimal.

Performance analysis of geometric variations in circular double gate MOSFETs at sub-7nm technology nodes

Circular Double Gate Transistors (CDGTs) is one of the alternative layout-based solutions to mitigate the short-channel effects with superior electrostatic controllability. In this article, TCAD based analysis of the CDGT at the 7 nm node for low-power (LP) applications is carried out and extracted electrical characteristics. The proposed CDGT device offers outstanding performance with ON current of 5.5 × 10−4 Amps, an OFF current of 5.9 × 10−12 Amps, and a corresponding switching ratio of 9.3 × 107 at 300 K. Furthermore, this study examined the performance of CDGT on device geometry by scaling of the gate length from 20 nm to 12 nm and Si thickness variation in the range of 5 nm–8 nm. Additionally, the influence of temperature variation is also studied on CDGT and extracted the temperature compensation point (TCP). Moreover, this simulation illustrates the use of CDGT devices for high switching applications with excellent ON current for lower sub 7 nm technology nodes.

Vertical tunneling FET with Ge/Si doping-less heterojunction, a high-performance switch for digital applications

A vertical tunneling field effect transistor composed of a doping-less tunneling heterojunction and an n+-drain is presented in this paper. Two highly-doped p+ silicon layers are devised to induce holes in an intrinsic source region. Due to employing a double gate configuration and Hafnium in the gate oxide, our proposed structure has an optimized electrostatic control over the channel. We have performed all the numerical simulations using Silvaco ATLAS, calibrated to the verified data of a device with the similar working principle. The impact of the wide range of non-idealities, such as trap-assisted tunneling, interface trap charges, and ambipolar conduction, is thoroughly investigated. We have also evaluated the impact of negative capacitance material to further improve our device switching characteristics. Introducing both n-channel and p-channel devices, and employing them into a 6T SRAM circuit, we have investigated its performance in terms of parameters like read and write SNM. The FOMs such as Ion = 34.4 µA/µm, Ion/Ioff = 7.17 × 107, and fT = 123 GHz show that our proposed device is a notable candidate for both DC and RF applications.

Exploring Performance and Reliability Behavior of Nanosheet Channel Thin-Film Transistors under Independent Dual Gate Bias Operation

In this work, the polycrystalline-silicon (poly-Si) thin-film transistor with an independent dual-gate (IDG) structure and ultra-thin nanosheet channel (∼4 nm) is fabricated to investigate the impacts of different dual-gate operation modes on device performance and reliability. Compared to the single top-gate (TG) operation mode, the double-gate (DG) operation mode exhibits superior threshold voltage (VTH), subthreshold swing, and saturation current in the device. In addition, the DG operation mode also shows better reliability behavior of positive gate bias stress (PGS) due to the enhanced control capability of the gate voltage on the channel potential. Under the single TG operation mode, the independent back-gate voltage (VBG) can effectively modulate the device’s VTH to meet circuit design requirements. Using a fixed positive VBG can not only reduce the VTH of the device, but also decrease the damage caused by the PGS on the device due to the buried channel effect generated by the ultra-thin nanosheet channel, which increases the coupling capacitance thickness between the buried channel and the top-gate oxide layer. On the contrary, using a negative VBG will enhance the PGS degradation of TG. Consequently, the positive VBG is suggested to lower the VTH and improve the PGS of the device.

Electrical Properties of Double-Gate Field-Effect Transistor Based on MA2N4 (M = Ti, Zr, and Hf; A = Si, Ge, and Sn) Monolayers

Electrical Properties of Double-Gate Field-Effect Transistor Based on MA₂N₄ (M = Ti, Zr, and Hf; A = Si, Ge, and Sn) Monolayers

A Simulation Study of the Effect of Trap Charges and Temperature on Performance of Dual Metal Strip Double Gate TFET

A Simulation Study of the Effect of Trap Charges and Temperature on Performance of Dual Metal Strip Double Gate TFET

Comprehensive analysis of single and double gate organic phototransistor

Comprehensive analysis of single and double gate organic phototransistor

Improved GaN-based Current Aperture Vertical Electron Transistor (CAVET)

The objectives of this research are to improve and optimize a vertically structure HEMT device based on AlGaN/GaN heterojunctions. This novel proposed structure with double gate command would allow for a better dispersion of the electric field, with peaks lower and farther from the surface than a lateral structure. The research focuses on estimating the performance of a GaN-based vertical structure called a "Current Aperture Vertical Electron Transistor (CAVET)" that combines a two-dimensional electron gas (2DEG) and a vertical structure with technology, operation, settings, and performance that can be seen in power applications. Performance operating at high frequencies and low power loss consumer, a device that will, therefore, lead function to best in electrical power and higher system efficiency with IDss equal 0.95 A, -6 V for pinch-off, fT/fMax are 110/250 GHz and 14 % for Drain-lag.