Double-gate Mode Research Articles

Double-gate structure enabling remote Coulomb scattering-free transport in atomic-layer-deposited IGO thin-film transistors with HfO2 gate dielectric through insertion of SiO2 interlayer

In this paper, high-performance indium gallium oxide (IGO) thin-film transistor (TFT) with a double-gate (DG) structure was developed using an atomic layer deposition route. The device consisting of 10-nm-thick IGO channel and 2/48-nm-thick SiO2/HfO2 dielectric was designed to be suitable for a display backplane in augmented and virtual reality applications. The fabricated DG TFTs exhibit outstanding device performances with field-effect mobility (μFE) of 65.1 ± 2.3 cm2V−1 s−1, subthreshold swing of 65 ± 1 mVdec−1, and threshold voltage (VTH) of 0.42 ± 0.05 V. Both the (μFE) and SS are considerably improved by more than two-fold in the DG IGO TFTs compared to single-gate (SG) IGO TFTs. Important finding was that the DG mode of IGO TFTs exhibits the nearly temperature independent μFE variations in contrast to the SG mode which suffers from the severe remote Coulomb scattering. The rationale for this disparity is discussed in detail based on the potential distribution along the vertical direction using technology computer-aided design simulation. Furthermore, the DG IGO TFTs exhibit a greatly improved reliability with negligible VTH shift of − 0.22 V under a harsh negative bias thermal and illumination stress condition with an electric field of − 2 MVcm−1 and blue light illumination at 80 °C for 3600 s. It could be attributed to the increased electrostatic potential that results in fast re-trapping of the electrons generated by the light-induced ionization of deep level oxygen vacancy defects.

Exploring Performance and Reliability Behavior of Nanosheet Channel Thin-Film Transistors under Independent Dual Gate Bias Operation

In this work, the polycrystalline-silicon (poly-Si) thin-film transistor with an independent dual-gate (IDG) structure and ultra-thin nanosheet channel (∼4 nm) is fabricated to investigate the impacts of different dual-gate operation modes on device performance and reliability. Compared to the single top-gate (TG) operation mode, the double-gate (DG) operation mode exhibits superior threshold voltage (VTH), subthreshold swing, and saturation current in the device. In addition, the DG operation mode also shows better reliability behavior of positive gate bias stress (PGS) due to the enhanced control capability of the gate voltage on the channel potential. Under the single TG operation mode, the independent back-gate voltage (VBG) can effectively modulate the device’s VTH to meet circuit design requirements. Using a fixed positive VBG can not only reduce the VTH of the device, but also decrease the damage caused by the PGS on the device due to the buried channel effect generated by the ultra-thin nanosheet channel, which increases the coupling capacitance thickness between the buried channel and the top-gate oxide layer. On the contrary, using a negative VBG will enhance the PGS degradation of TG. Consequently, the positive VBG is suggested to lower the VTH and improve the PGS of the device.

High-Performance Bidirectional Chemical Sensor Platform Using Double-Gate Ion-Sensitive Field-Effect Transistor with Microwave-Assisted Ni-Silicide Schottky-Barrier Source/Drain

This study proposes a bidirectional chemical sensor platform using ambipolar double-gate ion-sensitive field-effect transistors (ISFET) with microwave-assisted Ni-silicide Schottky-barrier (SB) source and drain (S/D) on a fully depleted silicon-on-insulator (FDSOI) substrate. The microwave-assisted Ni-silicide SB S/D offer bidirectional turn-on characteristics for both p- and n-type channel operations. The p- and n-type operations are characterized by high noise resistance as well as improved mobility and excellent drift performance, respectively. These features enable sensing regardless of the gate voltage polarity, thus contributing to the use of detection channels based on various target substances, such as cells, antigen-antibodies, DNA, and RNA. Additionally, the capacitive coupling effect existing between the top and bottom gates help achieve self-amplified pH sensitivity exceeding the Nernst limit of 59.14 mV/pH without any additional amplification circuitry. The ambipolar FET sensor performance was evaluated for bidirectional electrical characteristics, pH detection in the single-gate and double-gate modes, and reliability in continuous and repetitive operations. Considering the excellent characteristics confirmed through evaluation, the proposed ambipolar chemical sensor platform is expected to be applicable to various fields including biosensors. And through linkage with subsequent studies, various medical applications and precision detector operations for specific markers will be possible.

Performance of Source Follower Buffers Implemented with Standard and Strained Triple-Gate nFinFETs

In this work the application of standard and strained triple-gate FinFETs in unity-gain source-follower configuration is compared. The analysis is performed by evaluating the buffer voltage gain with respect to the fin width and channel length as well as the total harmonic distortion. It is demonstrated that the application of strained material in narrow FinFETs, when the devices are operating in double-gate mode, can be beneficial for the performance of buffers in any channel length. On the other hand, for triple-gate FinFETs or quasi-planar ones the degradation of the output conductance overcomes the transconductance improvements from strained material and the performance of standard buffers is better than of strained ones. Narrow strained buffers also offer better harmonic distortion.

Impacts of Bottom-gate Bias Control for Low-voltage Memory Operations of Charge-trap Memory Thin Film Transistors using Oxide Semiconductors

We fabricated and characterized the double-gate (DG) charge-trap memory thin film transistors (CTM-TFTs) using In-Ga-Zn-O active and ZnO charge-trap layers. The fabricated device exhibited a charge-trap-assisted memory window as wide as 13.8 V using a DG mode operation and a program/erase (P/E) speed faster than 10 μs. These memory device characteristics were examined by controlling the fixed bias voltage applied at the bottom gate (VSUBBG/SUB) and the capacitance coupling ratio between top and bottom gate insulators, which could be strategically designed with the DG configuration. The capacitance coupling ratio was varied by changing the bottom gate insulator (BGI) thickness between 50 and 100 nm. For the CTM-TFT with a BGI thickness of 100 nm, 3.1×10SUP6/SUP was obtained for the memory on/off ratio with P/E voltages of ± 15 V and a fixed VSUBBG/SUB of -3 V. Overall, our results suggest that the DG configuration can remarkably enhance the P/E speed and memory on/off ratio by suitably controlling the fixed VSUBBG/SUB conditions and the capacitance coupling ratio in CTM-TFTs.

Doping Dependent Assessment of Accumulation Mode and Junctionless FET for 1T DRAM

This paper demonstrates the use of double-gate accumulation mode (AM) and junctionless (JL) transistors for dynamic memory applications at 85 °C. The doping dependent assessments of AM and JL devices include an analysis of storage volume, carrier lifetime, and depth of potential well to determine characteristics of Dynamic Random Access Memory (DRAM). This paper shows significant impact of carrier lifetime for channel doping $({N}_{\text{d}}) \le 10^{ {18}}$ cm−3 on Retention Time (RT), while the depth of potential well is more critical at higher doping (>1018 cm−3). RT of ~2.5 s at 85 °C and ~4.5 s at 27 °C is achieved for gate length ( ${L}_{\text{g}}$ ) of 400 nm with ${N}_{\text{d}} = 10^{{17}}$ cm−3 which reduces to ~90 ms at 85 °C for ${L}_{\text{g}} = 25$ nm. This paper discusses the storage volume ( ${L}_{\text{g}} \times \text {film}$ thickness for a fixed volume with width of $1~ {\mu }\text{m}$ ) optimization to attain maximum retention. Insights and guidelines, as a function of doping and device dimensions, are outlined for dynamic memory applications.

High-Performance Double-Gate $\alpha $ -InGaZnO ISFET pH Sensor Using a HfO2 Gate Dielectric

In this paper, we present a high-performance double-gate (DG) amorphous indium–gallium–zinc–oxide ( $\alpha $ -InGaZnO) ion-sensitive field-effect transistor (ISFET) using three HfO2 gate dielectric thicknesses as a top gate (TG). The DG structure $\alpha $ -InGaZnO TFTs with a 40-nm TG HfO2 dielectric exhibited a small threshold voltage of 50 mV, a low subthreshold swing of 144.1 mV/decade, and a high ${I}_{{ \mathrm{\scriptscriptstyle ON}}}/{I}_{{ \mathrm{\scriptscriptstyle OFF}}}$ current ratio of $ {4.5} \times {10}^{7}$ . The $\alpha $ -InGaZnO ISFET prepared at the 40-nm HfO2 sensing membrane in the DG mode showed a pH sensitivity of 937 mV/pH, which is far more than the Nernst limit. The hysteresis and drift behaviors of DG ISFET fabricated with the 40-nm condition also showed relatively better chemical stability compared with other conditions.

Fin-Width Effects on Characteristics of InGaAs-Based Independent Double-Gate FinFETs

We report the characteristics of InGaAs-based independent double-gate FinFETs with Al2O3/LaAlO3 as gate dielectric. The device can be operated in three different modes ( i.e., single-, double-, and independent double-gate) made possible by the physically separated two sidewall gates. When the device is operated in the double-gate mode, it exhibits better performance in terms of the On/Off current ratio, subthreshold swing, Off current, and channel mobility than in the single-gate mode. In addition, independent double-gate operation makes it possible to modulate channel properties by applying a bias at the opposite gate via gate coupling effects. Our systematic measurements reveal that gate control and coupling effects are enhanced with reduced fin width.

On the Origin of Improved Charge Transport in Double-Gate In–Ga–Zn–O Thin-Film Transistors: A Low-Frequency Noise Perspective

Low-frequency noise (LFN) in double-gate (DG) In–Ga–Zn–O (IGZO) thin-film transistors (TFTs) is studied to investigate the origin of performance improvement. We found that thinning down the IGZO film enhances such improvements. With 7-nm IGZO, the mobility is raised by a factor of 3.77, and the subthreshold slope is reduced to 0.17 V/decade from single-gate to DG mode. Device simulations show that bulk transport inside IGZO film emerges as the two gates field effects get coupled. The LFN results reveal a transport transition from surface to bulk and disclose the superior bulk transport that experiences slight phonon scattering with a small Hooge parameter $\alpha _{H }= 4.44 \times 10^{\mathrm {-3}}$ , whereas the surface transport undergoes serious charge trapping with surface trap densities about $2 \times 10^{11}$ eV $^{-1}$ cm $^{-2}$ .

Investigation of Hole Mobility in Strained InSb Ultrathin Body pMOSFETs

Hole mobility in strained ultrathin body InSb-on-insulator (InSb-OI) devices is calculated by a microscopic approach. The anisotropic valence band structures, in consideration of quantum confinement, are obtained via solving the six-band k· p Schrödinger and Poisson equations self-consistently. Hole mobility is calculated using the Kubo-Greenwood formula accounting for nonpolar acoustic and optical phonons, polar optical phonons, and surface roughness scatterings. The models are calibrated and verified with experimental data. The influences of body thickness and strain effect, including both biaxial and uniaxial strains, are investigated in InSb-OI devices. Our results indicate that mobility degradation occurs in both single-gate (SG) and double-gate (DG) mode when body thickness scales down below a certain range. Moreover, mobility in the DG mode outperforms that in the SG for thick body thickness, but loses its superiority over SG for extremely thin body. Compressive strain is favorable to hole mobility. Furthermore, more enhancement is achieved by uniaxial strain than biaxial strain.

Self-Aligned Four-Terminal Planar Metal Double-Gate Low-Temperature Polycrystalline-Silicon Thin-Film Transistors for System-on-Glass

SUMMARY Self-aligned four-terminal (4T) planar metal double-gate (DG) polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) were fabricated on a glass substrate at a low temperature (LT), which is below 550 ◦ C, to realize high performance and low power dissipation system-onglass (SoG). The top gate (TG) and bottom gate (BG) were formed from tungsten (W); the BG was embedded in the glass substrate and the TG was fabricated by a self-alignment process using the BG as a photomask. This structure is called embedded metal double-gate (E-MeDG) in this paper. The poly-Si channel with lateral large grains was fabricated using a continuous-wave laser lateral crystallization (CLC). The self-aligned 4T E-MeDG LT poly-Si TFT, with a gate length of 5 m and TG and BG SiO2 thicknesses of 50 and 100nm, respectively, exhibited a subthreshold swing of 120mV/ dec and a threshold voltage (Vth) of 0.5V in the connecting DG mode; i.e. when TG is connected to BG. In the TG operation at various BG control voltage, a threshold voltage modulation factor ( = ∆Vth/∆ VBG) of 0.47 at negative BG control voltage and 0.60 at positive BG control voltage are demonstrated, which values are nearly equal to theoretical prediction of 0.40 and 0.75. Trend of subthreshold swing (s.s.) of TG operation under different BG control voltage are also consistent with theoretical prediction. In addition to TG operation, successful BG operation under various TG control voltages was confirmed. Field-effect mobility derived from gm also varied depending on control gate voltage. The high controllability of device parameter of individual LT poly-Si TFTs is caused by excellent crystalline quality of CLC poly-Si film and will enable us to

Deep-amorphization and solid-phase epitaxial regrowth processes for hybrid orientation technologies in SOI MOSFETs with thin body

Local Deep-Amorphization (DA) and subsequent Solid-Phase Epitaxial Regrowth (SPER) are envisioned for the co-integration of devices with hybrid surface orientation. The impact of these processes on the electrical characteristics of p-channel MOSFETs with 20nm thick film and HfO2 gate insulator/metal gate along the 〈110〉 direction on a (110) substrate is studied. No deterioration of transconductance and subthreshold swing at the front or back channels was induced by DA/SPER. The transconductance enhancement for the front and back channels on (110) substrates reaches +200% and +230% gain, respectively. For these transistors, we also discuss the variation of the external resistance and their operation in double-gate mode.

Electrostatics of JFET at 6 nm channel length: a simulation study

A junction field effect transistor (JFET) is studies as an alternative device for performing complementary logic currently limited to MOS. Complementary logic with cJFET bult using 60 nm lithography was reported recently. This summarises the simulation results of scaled n-channel JFET with a gate length of 6 nm. The JFET was operated in double gate mode. Results of this simulation study reveal that it is possible to scale JFET gate length to 6 nm operating at 0.5 V and achieve an ion/loff ratio greater than 5000. Threshold voltage can be varied by varying the channel profile. In Essence, JFET needs to be considered as a viable candidate for future scaling.

Origins of Performance Enhancement in Independent Double-Gated Poly-Si Nanowire Devices

In this paper, we characterize and compare the characteristics of a poly-Si nanowire (NW) device with independent double-gated configuration under different operation modes. In the device, the tiny NW channels are surrounded by an inverted-T-shaped gate and a top gate. It is found that the device under double-gate (DG) mode exhibits significantly better performance with respect to the two single-gate (SG) modes, as indicated by a higher current drive than the combined sum of the two SG modes and a smaller subthreshold swing of less than 100 mV/dec. Origins of such improvement have been identified to be due to the elimination of the back-gate effect as well as an enhancement in the effective mobility with the DG operation.

Influence of Fin Width and Channel Length on the Performance of Buffers Implemented with Standard and Strained Triple-Gate nFinFETs

In this work the application of standard and strained triple-gate FinFETs in unity-gain source-follower configuration is compared. The analysis is performed by evaluating the buffer voltage gain with respect to the fin width and channel length as well as the total harmonic distortion. It is demonstrated that the application of strained material in narrow FinFETs, when the devices are operating in double-gate mode, can be beneficial for the performance of buffers in any channel length. On the other hand, for triple-gate FinFETs or quasi-planar ones the degradation of the output conductance overcomes the transconductance improvements from strained material and the performance of standard buffers is better than of strained ones. Narrow strained buffers also offer better harmonic distortion.

Hole mobility enhancement by double-gate mode in ultrathin-body silicon-on-insulator p-type metal-oxide-semiconductor field-effect transistors

Hole mobility enhancement in double-gate (DG) ultrathin-body (UTB) silicon-on-insulator (SOI) p-type metal-oxide-semiconductor field-effect transistors (MOSFETs) is investigated systematically in comparison with single-gate (SG) UTB MOSFETs for various SOI thicknesses (TSOI) ranging from 2 to 30 nm. It is found that mobility in DG mode (μDG) is higher than that in SG mode (μSG) in all the measured ranges of TSOI and the surface carrier concentrations (Ns). In particular, enhancement of mobility of the sub-10-nm-thick TSOI devices is greater at higher Ns. As a result, it is demonstrated that μDG of the 8.1-nm-thick TSOI device is 12.9% greater than the universal mobility when Ns is 6×1012 cm−2. Higher μDG is attributed to the average effective mass reduction in DG mode because of the increased population in the light hole (LH) bands. Careful investigation also clarifies that mobility in the sub-10-nm-thick TSOI devices is enhanced greatly at higher Ns, since the DG mode-induced increase in the hole population in LH bands is enhanced at higher Ns; the reduction in the hole population in LH bands due to the high-Ns-enhanced carrier confinement in the normal direction is larger in SG mode than in DG mode.

Device characteristics of polymer dual-gate field-effect transistors

Dual-gate organic field-effect transistors (OFETs) were fabricated by solution processing using different p-type polymer semiconductors and polymer top-dielectric materials on prefabricated substrates with gold source-drain contacts defined by photolithography. The semiconductors and top dielectrics films were processed from solution by spin-coating and the silver top gate was applied by shadow mask evaporation. The dual-gate OFETs were characterized in double gate mode by sweeping the bottom gate bias from 40 to −50 V while fixing the top gate potentials, and vice versa. We demonstrate that the change in the threshold voltage of the bottom gate depends on the top gate bias with two linear relationships for two different regimes. The interpretations of the results, assuming that the mobilities of the top and bottom channels have similar magnitudes, and that the capacitance of the semiconductor layer is not negligible, indicated two distinct regimes for a dual-gate p-type OFET. 1. When one gate is positive, hence the respective channel is in depletion and no gate screening will occur, while the other gate is in accumulation regime, the field of the positive gate will penetrate to such a large extend that the channel in accumulation will be affected by both gates. 2. When both channels are in accumulation, the charges present in the channels will screen the respective gate potentials, hence both channels will operate individually and no mutual influences are observed. For a dual-gate OFET with its top channel in accumulation, we demonstrate a drop in the transconductance when the bottom gate potential becomes negative. This transition regime between both linear regimes is marked by a drop in the transconductance, where the bottom channel depends on the bottom gate only and the top channel will depend on both gates. The transition regime results from the fact that the charges accumulated in the bottom channel will start to screen the influence of the bottom gate potential on the top channel and the change in overall drain current will depend only on the change of the current of the bottom channel.

Experimental evidence of mobility enhancement in short-channel ultra-thin body double-gate MOSFETs by magnetoresistance technique

Double-gate transistor with ultra-thin body (UTB) has proved to offer advantages over bulk device for high-speed, low-power applications. There is thus a strong need to obtain an accurate understanding of carrier transport and mobility in such device. In this work, we report for the first time an experimental evidence of mobility enhancement in UTB double-gate (DG) MOSFETs using magnetoresistance mobility extraction technique. Mobility in planar DG transistor operating in single- and double-gate mode is compared. The influence of different scattering mechanisms in the channel is also investigated by obtaining mobility values at low temperatures. The results show a clear mobility improvement in double-gate mode compared to single-gate mode mobility at the same inversion charge density. This is explained by the role of volume inversion in ultra-thin body transistor operating in DG mode. Volume inversion is found to be especially beneficial in terms of mobility gain at low-inversion densities.

Evidence for mobility enhancement in double-gate silicon-on-insulator metal-oxide-semiconductor field-effect transistors

The methodology of mobility extraction from the Y-function or from the transconductance peak is revisited in the context of silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistors (MOSFETs). Based on a simple two-channel model, we discuss the biasing conditions that enable the Y-function to be applied to both single-gate (SG) and double-gate (DG) modes. Systematic mobility measurements in thick and ultrathin SOI transistors are presented for the front channel, back channel, and in quasi-double-gate mode. In SG-mode, the mobility is overestimated as soon as the opposite channel is activated. In partially depleted or relatively thick, fully depleted MOSFETs, the two channels are separated; hence, the total apparent mobility in DG mode is the sum of the front and back channel mobilities. By contrast, the two-channel model fails in ultrathin transistors, where the two channels become strongly coupled and volume inversion occurs. Volume inversion is reflected in a remarkable increase of the apparent mobility in DG mode.

Low Temperature Properties of Multi-Independent-Gate FET (MIGFET) Operating in Single-Gate and Double-Gate Modes

We investigated the temperature dependence of the electrical properties of the MIGFETs, such as the drain current, the transconductance, the threshold voltage, the subthreshold slope and the field effect mobility. Devices with a gate length of 30 nm, a gate width of 30 nm and a silicon fin height of 100 nm were characterized at a temperature range between 77 K and room temperature. The MIGFETs were operated and compared in double- gate (DG) and single-gate (SG) modes in order to reveal the coupling effects between the various gates. The subthreshold slope in SG mode improves with decreasing temperature, but remains far from the ideal value measured in DG mode. The variations of the transconductance and mobility as a function of temperature are explained by strong coupling and series resistance effects. In DG mode, the mobility is highly improved due to volume inversion and reduced surface roughness scattering.