Impacts of Bottom-gate Bias Control for Low-voltage Memory Operations of Charge-trap Memory Thin Film Transistors using Oxide Semiconductors

Abstract

We fabricated and characterized the double-gate (DG) charge-trap memory thin film transistors (CTM-TFTs) using In-Ga-Zn-O active and ZnO charge-trap layers. The fabricated device exhibited a charge-trap-assisted memory window as wide as 13.8 V using a DG mode operation and a program/erase (P/E) speed faster than 10 μs. These memory device characteristics were examined by controlling the fixed bias voltage applied at the bottom gate (VSUBBG/SUB) and the capacitance coupling ratio between top and bottom gate insulators, which could be strategically designed with the DG configuration. The capacitance coupling ratio was varied by changing the bottom gate insulator (BGI) thickness between 50 and 100 nm. For the CTM-TFT with a BGI thickness of 100 nm, 3.1×10SUP6/SUP was obtained for the memory on/off ratio with P/E voltages of ± 15 V and a fixed VSUBBG/SUB of -3 V. Overall, our results suggest that the DG configuration can remarkably enhance the P/E speed and memory on/off ratio by suitably controlling the fixed VSUBBG/SUB conditions and the capacitance coupling ratio in CTM-TFTs.