Double-diffused MOSFET Research Articles

Study of the SOI LDMOS With Low Conduction Loss and Less Gate Charge

This brief focuses on the silicon-on-insulator (SOI) split gate (SG) superjunction (SJ) lateral double-diffused MOSFET (LDMOS), in which the p-column is not only utilized to compensate the fields produced by the opposite charges in the drift region, but also further acting as an SG. The accumulation layers of an electron are formed in the drift region during the on-state, providing the lower resistance paths for electric current, which leads to a decrease in the specific on-resistance ( ${R}_{\text {ON,sp}}$ ). Furthermore, because of the semiconductor-insulator-semiconductor (SIS) capacitor, not all of the positive charges in the n-drift region intend to induce the negative charges on the gate, since there is a Miller capacitance, and thus the gate charge ( ${Q}_{G}$ ) is reduced with the weakened Miller effect. The simulation results indicate that comparing with the previous SOI SJ-LDMOS, ${R}_{\text {ON,sp}}$ and ${Q}_{G}$ can be reduced by 35% and 17%, respectively, leading to a 46% improvement of figure of merit for the proposed structure.

SiC/Si heterojunction VDMOS breaking silicon limit by breakdown point transfer technology

An innovative semiconductor power vertical double-diffused MOSFET (VDMOS) is proposed for the first time with the SiC/Si heterojunction at the P-base and N-drift region (called for SiC/Si VDMOS), which improves the trade-off between the breakdown voltage ( BV ) and specific on-resistance ( R on,sp ). The `soft' Si material has been combined with the `hard' SiC material to play their own advantages for SiC/Si VDMOS. The Si has been formed above the 6H-SiC substrate to make up the channel and source electrode, and the 6H-SiC is underneath the P-base to form the SiC/Si heterojunction. The novel terminal technology of breakdown point transfer has been advanced for the first time and applied to SiC/Si VDMOS, which transfers the breakdown point of SiC/Si VDMOS and improve the BV compared with Si VDMOS. The simulated results have been shown that the optimised BV of proposed SiC/Si VDMOS is increased from 226 to 578 V compared with the conventional Si VDMOS with the same drift region length, which is because the breakdown point is transferred from the higher electric field area with the maximum curvature radius to the low electric field area. The simulated R on,sp of SiC/Si VDMOS is 17.4 mΩ·cm 2 with the BV of 578 V, which is lower than that of 41.01 mΩ·cm 2 with the BV of 226V in Si VDMOS. The silicon limit relationship has been broken for SiC/Si VDMOS.

A Temperature-Dependent SiC MOSFET Modeling Method Based on MATLAB/Simulink

In this paper, a modeling method based on MATLAB/Simulink for a temperature-dependent SiC MOSFET in the entire working region was proposed. Using a supplementary test circuit, the output characteristics of a device in the saturated region were extracted. Based on these characteristics, the model covered the output characteristics of the device in the whole working region. From the output curves, three main parameters essential for modeling were derived. Based on the Si lateral double-diffused MOSFET model, a temperature-dependent static model of SCT20N120 was established by adding a temperature-dependent compensation voltage source to simulate the temperature characteristics of the threshold voltage and a temperature-dependent compensation current source to compensate for the drain current error in the linear region due to the differences in structure and material between Si and SiC. In addition, based on the gate equivalent circuit, the dynamic model of the target device was established. The temperature-dependent static simulation results could simulate the actual measured values well. Furthermore, based on the comparison between the dynamic simulation results involving the device’s turn-ON and turn-OFF process losses and the actual transient state losses derived from a double-pulse test under the conditions of $V_{\mathrm{ ds}}=300$ V, $I_{d}=15$ A, $R_{g\_{}exton}=18\,\,\Omega $ , and $R_{g\_{}extoff}=12\,\,\Omega $ at 200 °C, the maximum error was 6.7%.

An Improved SOI P-Channel LDMOS With High- ${k}$ Gate Dielectric and Dual Hole-Conductive Paths

An improved p-channel lateral double-diffused MOSFET (pLDMOS) with silicon-on-insulator substrate is proposed. On one hand, the improvement is attributed to a dielectric film with high permittivity (high-k), which is employed at the silicon surface to optimize the electric field distribution. Thus, the drift region dose could be increased, while its deviation has less influence on the breakdown voltage (BV). On the other hand, an additional pLDMOS is introduced to form another hole current path, which contributes to a decreased specific ON-resistance (R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on,sp</sub> ). The simulation results show that the proposed structure exhibits a BV of 366 V and an Ron,sp of 24 mΩ·cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , at a back gate bias of -200 V. Compared with the previous one, R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on,sp</sub> is decreased by 39%, and the dose deviation window of the drift region for ensuring the breakdown voltage above 300 V is relaxed from ±2% to ±5%.

Ultra-low specific on-resistance 700V LDMOS with a buried super junction layer

An ultra-low specific on-resistance 700 V lateral double-diffused MOSFET (LDMOS) with a buried super junction (BSJ) layer is proposed. [1–9] Buried P-pillars in the LDMOS can be depleted by neighboring N-pillars, overlying and underlying N-drift regions simultaneously, thus allowing a higher doping concentration. Consequently, the doping concentration of either the N-drift regions or N-pillars, or both, may also be increased therewith to compensate the surplus charges in the P-pillars. Compared with conventional surface super junction (SSJ) LDMOS, in which the super junction layer is implemented at the upper surface of the drift region, and P-pillars can only be depleted by the adjacent N-pillars and the N-drift regions beneath, the proposed novel LDMOS structure may have a lower specific on-resistance (Ron,sp) while maintain the same breakdown voltage (BV). Simulation results indicate that the Ron,sp of the novel structure is only 80.5 mΩ cm2 with a high BV of 750 V, which is reduced by 17% in comparison with the Ron,sp of a conventional SSJ LDMOS.

Novel Superjunction LDMOS (&gt;950 V) With a Thin Layer SOI

A novel superjunction (SJ) lateral double-diffused MOSFET (>950 V) with a thin layer SOI combining the advantage of low specific on-resistance ${R}_{\text {on,sp}}$ of the SJ and the high breakdown voltage ${V}_{\text {B}}$ of the thin SOI is proposed and experimentally demonstrated in this letter. Based on our previously developed equivalent substrate model, the optimized SJ endows the device with a respectably reduced ${R}_{\text {on,sp}}$ without sacrificing ${V}_{\text {B}}$ . Meanwhile, the thin layer SOI is designed with the enhanced dielectric layer field principle to carry out a high ${V}_{\text {B}}$ . The experimental results exhibit a ${R}_{\text {on,sp}}$ of 145 $\text{m}\Omega \cdot $ cm2 with a ${V}_{\text {B}}$ of 977 V. This represents a reduction in ${R}_{\text {on,sp}}$ by 18.1% when compared with the theoretical ${R}_{\text {on,sp}} \propto {V}_{\text {B}}^{{2.5}}\vphantom {^{^{^{^{}}}}}$ “silicon limit”.

Controlled Kink Effect in a Novel High-Voltage LDMOS Transistor by Creating Local Minimum in Energy Band Diagram

A new technique to control the kink effect in the high-voltage lateral double-diffused MOSFET (LDMOS) is presented in this paper. This technique produces a local minimum in the band diagram of the proposed structure, which causes the lower barrier height for the holes from the channel to the source region. So, the produced excess holes during the impact ionization process in the channel are reduced significantly. We have called the proposed structure as local minimum energy band LDMOS (LMEB-LDMOS) transistor. The LMEB-LDMOS structure contains modified source and drain regions. The modified source region creates a local minimum in the energy band diagram for absorbing the excess holes, and the modified drain region causes high breakdown voltage (462 V) and low specific on-resistance ( $5.1~\text {m}\Omega \cdot ~\text {cm}^{{{{2}}}})$ . Also, the drift region with lower doping density than drain is deleted in LMEB-LDMOS transistor. The simulation with 2-D ATLAS simulator shows that the proposed structure improves the device performance.

Analysis on the Rapid Recovery of Irradiated VDMOSFETs by the Positive High Electric Field Stress

High electric field stress (HEFS) and annealing effects on irradiated (by 60Co $\gamma$ -ray) vertical double-diffused MOSFETs (VDMOSFETs) are investigated. The behaviors of the oxide-trapped charges and interface traps during the stress are measured by using a simplified midgap technique. Rapid recovery of the threshold voltage ( $V_{\mathrm {th}}$ ) for the irradiated VDMOSFET is observed under a positive high electric field stress (PHEFS). The results show that the densities of oxide-trapped charges and interface traps decreased more rapidly for the PHEFS than that for postirradiation annealing. Repeated irradiation results of PHEFS-recovered VDMOSFETs indicate the possibility of reusing the irradiated VDMOSFETs.

Simulation-Based Study of Hybrid Fin/Planar LDMOS Design for FinFET-Based System-on-Chip Technology

A hybrid fin/planar lateral double-diffused MOSFET (LDMOS) design (hybrid FET) is proposed for the high-voltage input–output devices in a FinFET-based system-on-chip (SoC) technology. 3-D technology computer-aided design simulations show that a planar drift region and a planar drain region are advantageous for higher breakdown voltage (BV) to specific on-state resistance ( ${R}_{\text {on$\_{}$sp}})$ ratio (BV2/ ${R}_{\text {on$\_{}$sp}})$ . By slightly extending the planar portion of the semiconductor active region into the gated channel region, the theoretical limit of BV2/ ${R}_{\text {on$\_{}$sp}}$ for LDMOS can be surpassed. Hybrid FETs can be fabricated using a process flow that is compatible with the state-of-art FinFET SoC technology.

An ultra-low specific on-resistance double-gate trench SOI LDMOS with P/N pillars

A novel ultra-low specific on-resistance (Ron,sp) trench lateral double-diffused MOSFET with P/N pillars and dual trench gates (P/N DTG-T LDMOS) based on silicon-on-insulator technology is proposed in this paper. The new structure features dual trench gates and heavily doping P/N pillars. The P/N pillars are inserted into the drift region under the P-well. The P-pillar causes an assistant depletion effect on the drift region. The N-pillar can not only improve the breakdown voltage (BV) by modulating the electric field but also significantly reduce the Ron,sp by increasing the doping concentration of the drift region. Furthermore, the dual trench gates form dual conduction channels and the heavily doping N-pillar provides a lower resistance region for the carriers, which can both reduce the Ron,sp. Consequently, compared with the conventional trench LDMOS, a lower Ron,sp of 0.58 mΩ cm2 and a higher the figure of merit (FOM, FOM=BV2/Ron,sp) of 62.9 MW/cm2 are obtained for the P/N DTG-T LDMOS, which are improved by 74.8% and 308.4% respectively. Meanwhile, the BVs of the both structures are maintained at a same level of 190 V.

Numerical Investigation of High-Voltage Partial Buried P/N-Layer SOI LDMOS

High-voltage lateral double-diffused MOSFETs with partial buried P/N-type silicon layers (PBPL/PBNL) in silicon-on-insulator (SOI) technology are investigated numerically. In the lateral direction, the partial buried silicon layer (PBL) can introduce an additional electric field peak, which improves the surface electric field distribution and increases the charge accommodation in the drift region. Consequently, in the vertical direction, PBPL and PBNL can both induce higher electric field into the buried-oxide layer, and thus enhance the breakdown voltage (BV) significantly. Due to the higher electron concentration in the drift region, the ON-resistance ( ${R}_{ \mathrm{\scriptscriptstyle ON}}$ ) can be also reduced remarkably. The 2-D simulation results show that PBPL and PBNL SOIs can achieve BVs of 296 and 365 V, respectively, in comparison to the conventional SOI (BV ~ 225 V) and the buried N-layer SOI (BV ~ 231 V). In addition, by comparison with the conventional SOI, ${R}_{ \mathrm{\scriptscriptstyle ON}}$ can be reduced about 31.7% and 13.8% for PBPL and PBNL SOIs, respectively. Finally, hybrid PBPL/PBNL SOIs are studied and shown to be capable of further improving the device performance.

Multiple Trench Split-gate SOI LDMOS Integrated With Schottky Rectifier

In this paper, a multiple trench split-gate silicon-on-insulator (SOI) lateral double-diffused MOSFET with a Schottky rectifier (MTS-SG-LDMOS) is proposed and its characteristics are studied using 2-D simulations. The new structure features double oxide trenches, a floating polysilicon split-gate, and a Schottky rectifier. Each oxide trench includes a vertical field plate which enhances the depletion of the drift region and modulates the bulk electric field. As the simulation results, when compared to the conventional SOI LDMOS (C-LDMOS), the breakdown voltage in the MTS-SG-LDMOS increases from 297 to 350 V, the specific on-state resistance ( ${R} _{ \mathrm{\scriptscriptstyle ON},\mathsf {sp}}$ ) decreases from 142.9 to 48.2 $\text{m}\Omega \cdot \mathsf {cm}^{{\mathsf {2}}}$ , and the gate–drain charge ( ${Q} _{{\mathsf {gd}}}$ ) decreases from 19 to 9 pC. Moreover, the reverse recovery time of the proposed structure shows a 73.6% reduction as compared to the C-LDMOS device.

An improved SOI LDMOS with buried field plate

A silicon-on-insulator (SOI) lateral double-diffused MOSFET (LDMOSFET) with a buried field plate (BFP-LDMOS) is proposed. Its characteristics are studied using 2-D simulations. The proposed structure features double buried field plates which are surrounded by buried oxide (BOX) and connected to the source and drain electrode, respectively. The drain buried field plate (DBFP) prevents a premature breakdown at the interface of the silicon/BOX and enhances the dielectric field. The source buried field plate (SBFP) introduces a new electric-field peak and modulates the distribution of the horizontal electric field. In addition, the BFPs replace part of the BOX, which is useful to minimize self-heating effects (SHE). According to the simulation results, compared to a conventional SOI LDMOS (C-LDMOS), the breakdown voltage (BV) in the BFP-LDMOS increases from 128 V to 182 V. The specific on-state resistance (Ron,sp), however, decreases from 20.46 mΩ cm2 to 18.50 mΩ cm2. Moreover, the maximum lattice temperature at 1 mW/μm and Vgs = 10 V is reduced by 33.8 K compared to the C-LDMOS device.

New superjuction LDMOS with surface and bulk electric field modulation by buffered step doping and multi floating buried layers

A new superjunction lateral double diffused MOSFET with surface and bulk electric field modulation (SBEFM SJ-LDMOS) by applying of multiple floating buried layers and buffered step doping is proposed in this paper. The Multiple N-type floating buried layers are embedded in P-substrate, to reduce the amount of field crowding at N+/N-buffer/P-substrate junction by spreading the vertical depletion layer, which effectively improves the bulk electric field distribution in SJ-LDMOS, and the N+/N-buffer/P-substrate junction and the auxiliary MFB layers/substrate junctions jointly sustain a high vertical breakdown voltage (BV). In addition, based on the buffered step doping layer under the SJ layer, a uniform lateral electric field at the drift region surface of the device is obtained. Therefore, the bulk and surface electric field are both optimized simultaneously in SBEFM SJ-LDMOS. Simulated results show that compared with the conventional Buffered SJ-LDMOS and BSD SJ-LDMOS, the proposed SBEFM SJ-LDMOS improves BV by 131.7% and 80.4%, respectively, at the same drift region length and with low specific ON-resistance (RON,sp). SBEFM SJ-LDMOS exhibits excellent performance with the power figure-of-merit (FOM=BV2/RON,sp) of 13.07 MW/cm2.

3-D Edge Termination Design and ${R}_{ \mathrm{\scriptscriptstyle ON},\text {sp}}$ -BV Model of A 700-V Triple RESURF LDMOS With N-Type Top Layer

3-D edge termination design and analytic model for specific on-resistance ( ${R}_{ \mathrm{\scriptscriptstyle ON},\text {sp}})$ versus breakdown voltage (BV) of a 700-V triple reduced surface field lateral double-diffused MOSFET (LDMOS) with n-type top layer are presented in this paper. To eliminate the premature avalanche breakdown induced by the electric field crowding and the local charge imbalance in the transition region of the source-centered edge termination structure, 3-D numerical simulations and experiments are performed to investigate two crucial parameters ${L}_{1}$ and ${L}_{2}$ in the layout of the transition region. It is observed that optimal electric field distribution is obtained and breakdown positions are transferred to the active region at ${L}_{1} = 30~\mu \text{m}$ and ${L}_{2} = 1~\mu \text{m}$ . On the other hand, an analytic model is developed to describe the relation between ${R}_{ \mathrm{\scriptscriptstyle ON},\text {sp}}$ and BV, which is obtained as ${R}_{ \mathrm{\scriptscriptstyle ON},\text {sp}} = 5.93 \times 10^{-6} \times 22({T}/298)^{1.7} \times \text {BV}^{2}$ and theoretically verifies that the fabricated device has achieved optimized ${R}_{ \mathrm{\scriptscriptstyle ON},\text {sp}}$ and BV. Compared with our previous paper, the LDMOS experimentally demonstrated improved performance with ${R}_{ \mathrm{\scriptscriptstyle ON},\text {sp}}$ of 86.49 $\text{m}\Omega ~\cdot $ cm2 and BV of 805 V, which is leading performance for the 700-V applications in published data.

Modeling of Stacking Fault Expansion Velocity of Body Diode in 4H-SiC MOSFET

We present a model to explain forward voltage degradation of body diode in 4H-SiC MOSFET, and evaluate the velocity of SF expansion. First, by using in-situ photoluminescence (PL) observation, we investigated how a stacking fault (SF) expands from a basal plane dislocations (BPD) in the 4H-SiC epitaxial layer. Second, double-diffused MOSFETs were developed and measured before and after degradation. Then, the characteristics of the forward voltage degradation were modeled by a combination of PL imaging and electrical measurement, and the calculated characteristics are in good agreement with the measured ones. Finally, we tested the SiC MOSFETs under various stress conditions and evaluated the velocity of the SF expansion by calculation. This results indicate that the velocity of SF expansion increased with increasing forward current density and junction temperature.

New technique to extend the vertical depletion region at SOI-LDMOSFETs

In order to obtain an excellent performance for silicon-on-insulator lateral double-diffused MOSFET (SOI-LDMOSFET) transistors, we introduce a new technique to extend the depletion region along the vertical direction in the drift region. The proposed structure is called vertically depleted LDMOSFET (VD-LDMOSFET). The VD-LDMOSFET structure consists of a buried metal layer in the oxide region. The drift region of the VD-LDMOSFET is vertically depleted, not only from the buried oxide, but also by the incorporated metal layer in the buried oxide. Therefore, a higher drift doping density is achieved by an extension of the depletion region in the drift region and the on-state resistance $$({R}_{\mathrm{ON}})$$ reduces without degradation of the breakdown voltage. Also, an additional peak is created in the electric field distribution of the proposed structure and causes a reduction of the electric field peak near the gate and the drift region junction at the top surface of the device. Therefore, the breakdown voltage $$({V}_{\mathrm{BR}})$$ of the VD-LDMOSFET structure increases. The simulation results illustrate that by optimizing the doping density of the drift region and the dimensions of the metal layer in the proposed structure, the on-state resistance (28.9%) and the breakdown voltage (36.1%) are improved greatly and a superior tradeoff is achieved compared with a conventional SOI-LDMOSFET (C-LDMOSFET) structure.

Measurement and modeling of gate–drain capacitance of silicon carbide vertical double-diffused MOSFET

Silicon carbide (SiC) is considered as one of the key materials to realizing device operations in high-temperature, high-frequency, and high-power applications. When designing circuits in such applications, an accurate simulation model for SiC power MOSFETs is important. Among others, the gate–drain capacitance, Cgd, is particularly important in building the SiC MOSFET model because the capacitance significantly affects switching behavior of the device. In this paper, a Cgd model, which is based on a unified representation of surface potential, is proposed for enhancing the accuracy of circuit simulations. By considering the operation of vertical power SiC MOSFETs, the proposed capacitance model correctly accounts for the capacitance modulation effect due to the channel that is formed when the gate voltage is higher than the drain voltage. In addition, a Cgd measurement method is also proposed in order to characterize Cgd in a wider voltage range. Through experiments using a commercial SiC power MOSFET, it is demonstrated that the proposed model successfully approximates the capacitance in a wide range of bias voltages without stitching separate equations. It is also demonstrated that the proposed model is twice as accurate as the conventional one.

Novel lateral double-diffused MOSFET with vertical assisted deplete-substrate layer

Lateral double-diffused MOSFETs (LDMOS) are widely used in high voltage integrate circuits and smart power integrate circuits because of their lateral channels and their electrodes located on the surface of the device, thereby facilitating integration with other low-voltage circuits and devices, and they have become the core technology of the second electronic revolution. In order to optimize the breakdown characteristics and the performance of the LDMOS, in this paper, a novel LDMOS is proposed with the vertical assisted deplete-substrate layer (ADSL) on the basis of traditional LDMOS structure. The new ADSL layer makes the vertical depletion region below the drain expand to substrate excessively, thus introduces a new electric field peak at the bottom of the ADSL layer by using the electric field modulation effect, so that the vertical electric field is optimized. The ISE simulation results show that when the lengths of the drift region of ADSL LDMOS and traditional LDMOS are both 70 m, the breakdown voltage is increased from 462 V to 897 V, improved by about 94%. Also, the figure-of-merit (FOM) is upgraded from 0.55 MW/cm2 to 1.24 MW/cm2, increased by 125%. Therefore, the new structure ADSL LDMOS has a great improvement in device performance compared with that of the traditional LDMOS. Moreover, authors have studied the ADSL LDMOS from three parts, all of these confirm that the new structure has a great potential application in power device. Firstly, through the lateral surface electric field distributions and vertical electric filed distributions of conventional LDMOS and ADSL LDMOS, a new electric field peak at the bottom of the ADSL is introduced in the vertical direction. Secondly, the mechanism for the new structure can present a deeper understanding through the ADSL LDMOS concentration and structural parameter optimization process. The FOM is optimized when the drift region concentration and ADSL concentration are 1.81015 cm-3 and 6.51015 cm-3, respectively, and it can reach a best value when the ADSL length is 40 m. Thirdly, the ADSL layer is further partitioned and optimized. On the basis of the new structure, the breakdown voltage is increased to 938 V when the new structure is based on the dual partition, and in the triple partition the breakdown voltage reaches 947 V. In this paper, through simulations, the detailed analyses of the proposed new structure of the mechanism and its performance are conducted, and the breaking of the breakdown characteristics of silicon-based devices is of special significance for developing the lateral power devices.

Novel high-K with low specific on-resistance high voltage lateral double-diffused MOSFET**Project supported by the National Natural Science Foundation of China (Grant No. 61306094), the Project of Hunan Provincial Education Department, China (Grant No.13ZA0089), the Introduction of Talents Project of Changsha University of Science & Technology, China (Grant No. 1198023), and the Construct Program of the Key Discipline in Hunan Province,

A novel voltage-withstand substrate with high-K (HK, k > 3.9, k is the relative permittivity) dielectric and low specific on-resistance (Ron,sp) bulk-silicon, high-voltage LDMOS (HKLR LDMOS)is proposed in this paper. The high-K dielectric and highly doped interface N+-layer are made in bulk silicon to reduce the surface field drift region. The high-K dielectric can fully assist in depleting the drift region to increase the drift doping concentration (Nd) and reshape the electric field distribution. The highly doped N+-layer under the high-K dielectric acts as a low resistance path to reduce the Ron,sp. The new device with the high breakdown voltage (BV), the low Ron,sp, and the excellent figure of merit (FOM = BV2/Ron,sp) is obtained. The BV of HKLR LDMOS is 534 V, Ron,sp is 70.6 mΩ·cm2, and FOM is 4.039 MW·cm−2.