Measurement and modeling of gate–drain capacitance of silicon carbide vertical double-diffused MOSFET

Abstract

Silicon carbide (SiC) is considered as one of the key materials to realizing device operations in high-temperature, high-frequency, and high-power applications. When designing circuits in such applications, an accurate simulation model for SiC power MOSFETs is important. Among others, the gate–drain capacitance, Cgd, is particularly important in building the SiC MOSFET model because the capacitance significantly affects switching behavior of the device. In this paper, a Cgd model, which is based on a unified representation of surface potential, is proposed for enhancing the accuracy of circuit simulations. By considering the operation of vertical power SiC MOSFETs, the proposed capacitance model correctly accounts for the capacitance modulation effect due to the channel that is formed when the gate voltage is higher than the drain voltage. In addition, a Cgd measurement method is also proposed in order to characterize Cgd in a wider voltage range. Through experiments using a commercial SiC power MOSFET, it is demonstrated that the proposed model successfully approximates the capacitance in a wide range of bias voltages without stitching separate equations. It is also demonstrated that the proposed model is twice as accurate as the conventional one.