Double Base Number System Research Articles

Novel low PDP CMOS Double-Base Multiplier

Multipliers play a vital role on digital low power communication system. This present study introduced a new novel strategy of multiplication that can improve speed-power efficiency with a double-based number system multiplier. Designing with a Double base number system multiplier is a suitable alternation due to its two important properties redundancy & sharpness. Extensive simulations has been done to examine the competency of proposed designs under three different test conditions to test . It then compares some of the critical parameters with excising single base number system (i.e. Binary number system) & Multi-value number system (i.e. Ternary Number system). All the design optimization & evaluations performed are based on the BSIM4 device parameter of TSMC 0.18µm CMOS technology with 0.9V supply at 27oC temperature using S. Edit of Tanner EDA..

A New Algorithm to Derive High Performance and Low Hardware Cost DCT for HEVC

Owing to its good compression ability, discrete cosine transform (DCT) is widely used in signal processing, including high-efficiency video coding (HEVC). For efficient implementation, approximate DCTs and integer DCTs were proposed, but the challenge in the tradeoff between coding performance and implementation cost always exists. To solve this problem, this article proposes a new algorithm to derive Int-DCT with good coding performance and low hardware cost. To address the multiobjective optimization problem, we extract information from the initially shortlisted transform matrices to derive the weighting factors for the different matrices properties. Those properties having a higher impact to the performance are assigned with higher weights and vice versa. Subsequently, an efficient search algorithm is proposed to shortlist those candidates which can lead to better coding performance evaluated by the proposed measure. Last but not the least, a splitting method is proposed to search the efficient extended double-base number system (EDBNS) representation of the coefficients for hardware implementation and select the solution which encounters the lowest cost. The experimental results in ASIC demonstrate that the implementation area and power cost of designs by the new algorithm are reduced by at least 11.1% and 17.5% for 32-point transform, respectively, over other competing algorithms. Meanwhile, the transforms generated by the proposed algorithm causes negligible impact to coding performance compared to the original transforms in HEVC.

Tight lower bound for average number of terms in optimal double-base number system using information-theoretic tools

We propose to use information-theoretic tools for analyzing the number of terms in the optimal double-base number system (DBNS). Most previous works analyze the largest number we obtain from the optimal DBNS for 0≤m<2n. They show that the largest number would be in Θ(n/log⁡n). On the other hands, when one analyze the performance of a cryptographic algorithm, it is more common to consider the average number of terms. One believes that we may be able have smaller asymptotic number for the average number. Unfortunately, using tools in information theory, we show in this paper that the average number is also in Θ(n/log⁡n).

A New Architecture for Transformation of Binary to Double Base Number System (DBNS) with Bases 2 and 5 using Different Search Algorithms

In this paper a new architecture for the transformation of binary to double base number system (DBNS) with bases 2 and 5 using different search algorithms has been presented. Nowadays the DBNS is becoming popular among the other non-binary number systems for their competences of carrying out multiplication operation proficiently. The DBNS has the major problem which is associated with this number system is the transformation from binary data to DBNS data despite the various advantages of the DBNS. A number of schemes are there to transform the binary number into the DBNS. By observing these matters a new transformation scheme has been presented for the transformation of binary data into a single index pair (i.e., singledigit) DBNS data with bases 2 and 5.

Performance Analysis of FPGA Based MAC Unit using DBTNS Multiplier &amp; TRNS Adder for Signal Processing Algorithm

Digital signal processing (DSP) algorithms are actually nothing but sum of product. So, they are computationally intensive. All the mathematical tasks related to DSP algorithm are based on multiplication and addition. So, the implementations of DSP algorithms-based applications extensively require multiplier and adder. Due to extensive use of multiplication and addition operation, speed up cannot be achieved. Designing the high-performance adder and multiplier are primary objective for implementing high performance signal processing applications. This hindrance can be removed by Multiply-Accumulate Unit (MAC). The special feature of a MAC unit is its ability to perform single cycle multiplication and addition operation.The performance of MAC Unit can be improved by using non-binary number system. Ternary value logic (TVL) has the ability to offer several advantages over conventional binary number system like reduce chip area, reduce overall delay. TVL can switch between three levels, such levels denoted by 0, 1, 2. As Residue Number Systems (RNS) can perform carry arithmetic operations, high performance adder can be implemented using RNS in TVL domain (TRNS). Partial product free multiplication can be implemented by using Double Base Number System in TVL domain (DBTNS). Double Base Ternary Number System (DBTNS) multiplier can perform better than conventional TVL multiplier. A MAC unit is used to perform the multiplication and accumulator operations together to avoid unnecessary overhead on the processor in terms of processing time and the on-chip memory requirements. Keeping in view of these issues, a new architecture is proposed for implementing high performance MAC unit for DSP applications. In this paper, a new approach of designing MAC unit is instigated using DBTNS multiplier and TRNS adder. A major bottleneck of implementing this architecture is the complexity involved in converting TVL to DBTNS in initial stage and converting TRNS to TVL in final stage. The performance of Ternary Residue Number Systems (TRNS) system depends on selection of moduli because selection of moduli is not properly maintained then it will affect system speed, dynamic range and hardware complexity. Proposed MAC unit is mapped on field programmable gate array (FPGA) for analysis its performance.

Shared Processing Element Architecture for An Area and Power Efficient FIR Filter Design using Double Base Number System

In this paper, a modification to the double base number system (DBNS) architecture is proposed and implemented. The proposed design named Shared Processing Element Architecture (SPEA) utilizes the processing element based on time multiplexing. The architecture is area And power efficient when implemented for an FIR Filter Design Using Double Base Number System. The work utilizes the double base number system (DBNS) to encapsulate the binary shifts in tandem with several most frequently encountered common sub expressions but with the proposed modified architecture. The blocks are implemented and simulation outputs are observed. Timing and power analysis, analyzed through the Quartus 9.1-Cyclone II device family under the 90nm technology is done. In the future the FIR filter structure utilizing the proposed methodology will be implemented for adaptive filters.

Efficient Double Bases for Scalar Multiplication

In this paper we present efficient algorithms to take advantage of the double-base number system in the context of elliptic curve scalar multiplication. We propose a generalized version of Yao's exponentiation algorithm allowing the use of general double-base expansions instead of the popular double base chains. We introduce a class of constrained double base expansions and prove that the average density of non-zero terms in such expansions is O( log k/ log log k) for any large integer k. We also propose an efficient algorithm for computing constrained expansions and finally provide a comprehensive comparison to double-base chain expansions, including a large variety of curve shapes and various key sizes.

Comparative Study and Analysis of Performances among RNS, DBNS, TBNS and MNS for DSP Applications

This paper presents a comparative study of the performances of arithmetic units, based on different number systems like Residue Number System (RNS), Double Base Number System (DBNS), Triple Base Number System (TBNS) and Mixed Number System (MNS) for DSP applications. The performance analysis is carried out in terms of the hardware utilization, timing complexity and efficiency. The arithmetic units based on these number systems were employed in designing various modulation schemes like Binary Frequency Shift Keying (BFSK) modulator/demodulator. The analysis of the performance of the proposed modulator on above mentioned number systems indicates the superiority of other number systems over binary number system.

Two Lower Bounds for Shortest Double-Base Number System

In this letter, we derive two lower bounds for the number of terms in a double-base number system (DBNS), when the digit set is {1}. For a positive integer n, we show that the number of terms obtained from the greedy algorithm proposed by Dimitrov, Imbert, and Mishra [1] is $\Theta\left(\frac{\log n}{\log \log n}\right)$. Also, we show that the number of terms in the shortest double-base chain is Θ(log n).

Novel Design Algorithm for Low Complexity Programmable FIR Filters Based on Extended Double Base Number System

Coefficient multipliers are the stumbling blocks in programmable finite impulse response (FIR) digital filters. As the filter coefficients change either dynamically or periodically, the search for common subexpressions for multiplierless implementation needs to be performed over the entire gamut of integers of the desired precision, and the amount of shifts associated with each identified common subexpression needs to be memorized. The complexity of a quality search is thus beyond the existing design algorithms based on conventional binary and signed digit representations. This paper presents a new design paradigm for the programmable FIR filters by exploiting the extended double base number system (EDBNS). Due to its sparsity and innate abstraction of the sum of binary shifted partial products, the sharing of adders in the time-multiplexed multiple constant multiplication block of the programmable FIR filters can be maximized by a direct mapping from the quasi-minimum EDBNS. The multiplexing cost can be further reduced by merging double base terms. Logic synthesis results on more than one hundred programmable filters with filter taps ranging from 10 to 100 and coefficient word lengths of 8, 12, and 16 bits show that the average logic complexity and critical path delay of the programmable FIR filters designed by our proposed algorithm have been reduced by up to 47.81% and 14.32%, respectively over the existing design methods.

Radix- &lt;inline-formula&gt; &lt;tex-math notation="TeX"&gt;$2^{r}$&lt;/tex-math&gt;&lt;/inline-formula&gt; Arithmetic for Multiplication by a Constant

In this brief, radix- $2^{r}$ arithmetic is explored to minimize the number of additions in the multiplication by a constant. We provide the formal proof that, for an $N$ -bit constant, the maximum number of additions using radix- $2^{r}$ is lower than Dimitrov's estimated upper bound $2 \cdot N/\log(N)$ using the double-base number system (DBNS). In comparison with the canonical signed digit (CSD) and the DBNS, the new radix- $2^{r}$ recoding requires an average of 23.12% and 3.07% less additions for a 64-bit constant, respectively.

New and Improved Methods to Analyze and Compute Double-Scalar Multiplications

We address several algorithms to perform a double-scalar multiplication on an elliptic curve. All the methods investigated are related to the double-base number system (DBNS) and extend previous work of Doche et al. [25]. We refine and rigorously prove the complexity analysis of the joint binary-ternary (JBT) algorithm. Experiments are in line with the theory and show that the JBT requires approximately 6 percent less field multiplications than the standard joint sparse form (JSF) method to compute [n]P + [m]Q. We also introduce a randomized version of the JBT, called JBT-Rand, that gives total control of the number of triplings in the expansion that is produced. So it becomes possible with the JBT-Rand to adapt and tune the number of triplings to the coordinate system and bit length that are used, to further decrease the cost of a double-scalar multiplication. Then, we focus on Koblitz curves. For extension degrees enjoying an optimal normal basis of type II, we discuss a Joint τ-DBNS approach that reduces the number of field multiplications by at least 35 percent over the traditional τ-JSF. For other extension degrees represented in polynomial basis, the Joint τ-DBNS is still relevant provided that appropriate bases conversion methods are used. In this situation, tests show that the speedup over the τ-JSF is then larger than 20 percent. Finally, when the use of the τ-DBNS becomes unrealistic, for instance because of the lack of an efficient normal basis or the lack of memory to allow an efficient conversion, we adapt the joint binary-ternary algorithm to Koblitz curves giving rise to the Joint τ-τ method whose complexity is analyzed and proved. The Joint τ-τ induces a speedup of about 10 percent over the τ-JSF.

Scalar multiplication for twisted Edwards curves using the extended double-base number system

Scalar multiplication for twisted Edwards curves using the extended double-base number system

Performance analysis of a FPGA based novel binary and DBNS multiplier

Designing high performance Software Defined Radio (SDR) with low power and flexibility is a major challenge. While the high performance DSP processors are unable to meet the speed requirements of these SDRs, System on chips (SOCs) are also not suitable because of their limited flexibility. Recently dynamically reconfigurable FPGAs have emerged as high performance programmable hardware to execute highly parallel, computationally intensive signal processing functions efficiently. Since basic intention of an SDR is to implement different modulation / demodulation schemes and basic building blocks for such schemes are signal processing functions, FPGAs have become an important component for implementing these. However, the effectiveness of such an approach with respect to cost, performance and flexibility need to be examined. Double Base Number Systems (DBNS) have been gaining attention for compute intensive applications in signal processing because of their higher performance in arithmetic operations in general and particularly multiplication. Keeping these issues in view, this paper aims to present a new Software defined Radio. To Enhance the performance of the proposed architecture , analysis have been done employing both single index and multiple indices DBNS multipliers. Experiments and analysis on performance have also been done with its binary counterpart. Both DBNS and binary based architecture were implemented on Xilinx virtex iv FPGA using xilinx ISE 9.1 i.

A new algorithm for computing triple-base number system

We introduce here a generalized method a new Algorithm to find Triple-Base number system and Triple-Base chain and hence in turn Single Digit Triple-Base number system(SDTBNS). The proposed method is not only simpler and faster than the Algorithms to find Double-Base number system or Double-Base chain, experimentally it also returns a shorter length of Triple-Base chain which in turn reduces the size of the look-up-table to find out SDTBNS. The complexity analysis and experimental results shows the novelty of the proposed Algorithm. Moreover when the proposed method is applied to find scalar multiplication in case of Elliptic Curve Cryptography and coefficient multiplication in case of designing digital filter, its efficiency also proves its novelty. Here we have used third base as 5 because when it is multiplied by 2 gives 10 which can be efficiently used for decimal shifting, i.e. if an integer 'n' can be represented in SDTBNS form, then n/10 x or nx10 x can also represented in SDTBNS only by diving or multiplying 'n' by 10.

Design of High Performance Multiplier Unit using SDTBNS for DSP Applications

In this paper, a new number system “Single Digit Triple Base Number System (SDTBNS)” using 2, 3 and 5 as the bases have been introduced. Advantages of SDTBNS over Single Digit Double Base Number System (SDDBNS) have been discussed here. Dynamic range of the numbers represented in SDTBNS has also been dealt with in details. Analysis on complexity of the multiplication unit and execution time reveal the novelty of the proposed number system. Application of this number system in digital signal processing(DSP) has been explored and an efficient implementation of linear convolution has been presented.

A new architecture for FPGA implementation of a MAC unit for digital signal processors using mixed number system

Execution of arithmetic operations at very high speed in real time is the major concern in digital signal processing (DSP) because DSP algorithms are computation intensive. In recent times, Residue Number Systems (RNS) are considered as alternative to binary number system because of their capabilities of performing "carry-free" addition and Multiplication. Double Base Number Systems (DBNS), another non-binary number systems are also increasingly becoming attractive for signal processing applications due to their capabilities of handling arithmetic operations, particularly multiplication efficiently. However, the complexity involved in converting binary to DBNS becomes a major bottleneck and the efficiency of performance decreases considerably due to large conversion time. So RNS Adder and DBNS Multiplier can be used to implement multiply &amp; accumulate (MAC) units. Because RNS adders are less complex and faster compared to DBNS and DBNS multipliers are efficient compared to RNS multiplier. MAC units are the key units in Digital Signal Processors. In this paper we have shown how FIR filter can be implemented using the proposed "Mixed Number System MAC units".

New Multiplier for a Double-Base Number System Linked to a Flash ADC

The double-base number system has been used in digital signal processing systems for over a decade because of its fast inner product operation and low hardware complexity. This letter proposes an innovative multiplier architecture using hybrid operands. The multiplier can easily be linked to flash analog-to-digital converters or digital systems through a double-base number encoder (DBNE) for realtime signal processing. The design of the DBNE and the multiplier enable faster digital signal processing and require less hardware resources compared to the binary processing method.

New Multiplier for a Double-Base Number System Linked to a Flash ADC

The double-base number system has been used in digital signal processing systems for over a decade because of its fast inner product operation and low hardware complexity. This letter proposes an innovative multiplier architecture using hybrid operands. The multiplier can easily be linked to flash analog-to-digital converters or digital systems through a double-base number encoder (DBNE) for realtime signal processing. The design of the DBNE and the multiplier enable faster digital signal processing and require less hardware resources compared to the binary processing method.

A new architecture for FPGA based implementation of conversion of binary to double base number system (DBNS) using parallel search technique

Compute intensive signal Processing Algorithms demand efficient execution of high performance arithmetic operations. Since, double base number system (DBNS) offers high performance arithmetic units, it is gaining attention to many researchers .However, the advantage of DBNS can not be exploited due to large conversion time from binary to DBNS. Keeping this issue in view, this paper presents a novel conversion scheme using parallel search technique.