Shared Processing Element Architecture for An Area and Power Efficient FIR Filter Design using Double Base Number System

Abstract

In this paper, a modification to the double base number system (DBNS) architecture is proposed and implemented. The proposed design named Shared Processing Element Architecture (SPEA) utilizes the processing element based on time multiplexing. The architecture is area And power efficient when implemented for an FIR Filter Design Using Double Base Number System. The work utilizes the double base number system (DBNS) to encapsulate the binary shifts in tandem with several most frequently encountered common sub expressions but with the proposed modified architecture. The blocks are implemented and simulation outputs are observed. Timing and power analysis, analyzed through the Quartus 9.1-Cyclone II device family under the 90nm technology is done. In the future the FIR filter structure utilizing the proposed methodology will be implemented for adaptive filters.