A new architecture for FPGA implementation of a MAC unit for digital signal processors using mixed number system

Abstract

Execution of arithmetic operations at very high speed in real time is the major concern in digital signal processing (DSP) because DSP algorithms are computation intensive. In recent times, Residue Number Systems (RNS) are considered as alternative to binary number system because of their capabilities of performing "carry-free" addition and Multiplication. Double Base Number Systems (DBNS), another non-binary number systems are also increasingly becoming attractive for signal processing applications due to their capabilities of handling arithmetic operations, particularly multiplication efficiently. However, the complexity involved in converting binary to DBNS becomes a major bottleneck and the efficiency of performance decreases considerably due to large conversion time. So RNS Adder and DBNS Multiplier can be used to implement multiply & accumulate (MAC) units. Because RNS adders are less complex and faster compared to DBNS and DBNS multipliers are efficient compared to RNS multiplier. MAC units are the key units in Digital Signal Processors. In this paper we have shown how FIR filter can be implemented using the proposed "Mixed Number System MAC units".